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Introduction - If you have any usage issues, please Google them yourself
Note 1: contains a comprehensive statement can not, please amend Note 2: Some PLD only permit I/O port of external tri-state, does not support internal tri-state, the use of when we should pay attention Note 3: the design of RAM
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Packet : 93317464vhdl.rar filelist
VHDL\LED七段译码.txt
VHDL\readme.txt
VHDL\VHDL程序范例使用说明.doc
VHDL\波形发生器(含test beach).vhd
VHDL\布斯乘法器.txt
VHDL\步进电机控制器.vhd
VHDL\带load、clr等功能的寄存器.vhd
VHDL\带莫尔_米勒输出的状态机.txt
VHDL\带三态输出的8位D寄存器:74374.txt
VHDL\带同步复位的状态机.txt
VHDL\地址译码(for m68008).txt
VHDL\多路选择器(使用when-else语句).txt
VHDL\各种功能的计数器.vhd
VHDL\汉明纠错吗编码器.txt
VHDL\汉明纠错吗译码器.txt
VHDL\加法器描述.txt
VHDL\加法器源程序.v
VHDL\加法器源程序.vhd
VHDL\简单的12位寄存器.vhd
VHDL\简单的锁存器.vhd
VHDL\经典双进程状态机(含test beach).txt
VHDL\米勒型状态机.txt
VHDL\莫尔型状态机1.txt
VHDL\莫尔型状态机2.txt
VHDL\三人表决器(三种不同的描述方式).txt
VHDL\三态总线(注2).txt
VHDL\使用变量的状态机.txt
VHDL\使用列举类型的状态机.vhd
VHDL\双2-4译码器:74139.txt
VHDL\双向总线(注2).txt
VHDL\四D触发器74175.txt
VHDL\通用寄存器.txt
VHDL\伪随机比特发生器.txt
VHDL\伪随机数产生器.vhd
VHDL\相应加法器的测试向量(test bench).vhd
VHDL\一个简单的UART.vhd
VHDL\一个简单的状态机.vhd
VHDL\一个游戏程序.vhd
VHDL\移位寄存器:74164.txt
VHDL\直流电机控制器.vhd
VHDL\最高优先级编码器.txt
VHDL\8位相等比较器.txt
VHDL\8位总线收发器:74245.txt
VHDL\fifo存储器举例:(注3).txt
VHDL
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