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【Scanner】 code DL : 0: 网络扫描器、可以进行TCP、SYN、扫描,可自定义IP和端口-Network Scanner can be TCP, SYN, scanning, customizable IP and port
Update : 2024-05-18 Size : 94208 Publisher : Fisher
【Internet-Network】 S-scanner DL : 0: 内置超强SYN扫描工具S扫描器，内置SYN安装，速度很快，非常实用-Built-in super SYN scan tool S scanner, built-in SYN install, very fast, very practical
Update : 2024-05-18 Size : 261120 Publisher : C G
【OS program】 WIN32-syn-memshare DL : 0: IPC 内存共享，实现多个进程间通讯,同时包含进程同步，本例程包含读写两个进程，测试通过-The IPC memory sharing, communicating between multiple processes, contain process synchronization at the same time, read and write this routine includes two processes, the test pass
Update : 2024-05-18 Size : 41984 Publisher : 张毅
【Exploit】 MySYN1 DL : 0: C++ 生成 SYN flood泛洪攻击-C++ generate flood SYN flood attack
Update : 2024-05-18 Size : 2048 Publisher : 李阳
【Communication】 main_no_offset_2 DL : 0: 假设截获了一段短波数字通信的信号，要求解调出最终的信息，每组解调出来后，将10组信息组合起来，恢复最终的信源输出数据。先验信息：两组数据文件，编号为1、2，每组I、Q两路存放，格式为“int16”，采样率为9600Sa/s，其中第一组为单径情况，第二组为多径情况。参数符合MIL-STD-188-110A标准；同步序列为syn=seq.dat，BPSK调制；接收机频率稳定度高于1e-6。文件中有效信息总长度为333.75s，其中同步头长为5/12s，每时隙1/6s，训练序列占10 ，在数据之前；交织方式为全交织，矩阵交织，列为1000，在比特级进行；纠错码码率为1/2；调制方式为BPSK、QPSK和8PSK中的一种，映射方式为二进制，BPSK相位偏移为0，其余两种为。 -Suppose intercepted signal for a period of short-wave digital communications requires final demodulated information after each demodulated, combining 10 group information, to restore the final output data source. Priori information: two sets of data file, numbered 1, 2, each I, Q two-way storage, the format is int16 , sampling rate 9600Sa/s, where the first group is a single path, the second group multipath situation. Parameters meet MIL-STD-188-110A standard Synchronization sequence syn = seq.dat, BPSK modulation The frequency stability of the receiver is higher than 1e-6. File payload total length of 333.75s, wherein the synchronization header length is 5/12s, each time slot 1/6s, accounting for 10 of the training sequence, before the data Interleaving for the whole interleaving matrix interleaving, as 1000, carried out at the bit level Error correction code rate of 1/2 The modulation scheme is BPSK, QPSK and 8PSK one, a binary mapping, the BPSK phase offset is 0, the
Update : 2024-05-18 Size : 4096 Publisher : suxiaogua
【Crack Hack】 dx DL : 0: 上线主机稳定，连接速度快，超强攻击效果，网吧经常掉线？网站经常被攻击？站长很闹心！服务器经常连接不上？非常郁闷！你们很有可能遭受竞争对手的恶意攻击leader网络工作室成立于2009年，自成立以来一直致力于网络软件开发，网站与服务器防护以及网络压力DDOS等领域的技术发展与创新。现在将最新研发的成果放出来竭诚服务于网站站长与服务器管理员 1.穿透cc压力测试集合了市面上所有攻击软件优点取得了革命性突破(独立编写代码.很有效的防止放火墙公司修改参数进行防御攻击.) 2.软件控制端以及服务端,升级及时,尽量保证客户肉鸡丢失.减少不必要的损失! 3.改善了传统攻击软件的内核缺陷.增加了优化了肉鸡连接服务端线程.减少了占资源等问题....更多功能请看演示动画..... 4.服务端：重启后无进程，非注入，启动速度快，文件体积30K，方便下载。攻击完全不占CPU，不卡。 5.攻击模式：ICMP洪水SYN洪水、TCP洪水
Update : 2024-05-18 Size : 664576 Publisher : 冰
【Software Engineering】 power_machines DL : 0: power syn machine with avr and governer
Update : 2024-05-18 Size : 32768 Publisher : omidsyt
【VHDL-FPGA-Verilog】 gpio-master DL : 0: 基于WISHBONE总线接口的GPIO模块verilog代码实现，包含详细GPIO定义文档，testbench，RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
Update : 2024-05-18 Size : 419840 Publisher : lv
【matlab】 nlcg6-syn-inv DL : 0: NLCG6生成反演数据以及加入噪声的matlab程序-NLCG6 inversion data generated and added to the noise matlab program
Update : 2024-05-18 Size : 4096 Publisher : 苏琦
【Program doc】 5237234 DL : 0: 均匀圆阵列理论推到，老外教材一部分，费老大劲找到的。希望对你有用。-In this chapter, we present an overview of the basics of circular array theory. This will serve as a background to the chapters on conformal array characteristics, design, and syn- thesis. We will also discuss the concept of phase modes, which is a useful tool for the understanding of the performance of circular arrays. I
Update : 2024-05-18 Size : 531456 Publisher : 赵杰
【Internet-Network】 SYNFLOOD DL : 0: syn ddos flood 工具源代码-syn ddos flood source code
Update : 2024-05-18 Size : 2048 Publisher : anonymouss
【Other】 Optimal-controllers-designs-for-automatic-reactiv DL : 0: The paper presents the bacterial foraging optimization algorithm (BFOA) and particle swarm optimiza- tion (PSO) algorithm based robust controllers for voltage deviations due to the variation of reactive power in an isolated wind-diesel hybrid power system. The isolated wind-diesel system consists of wind energy conversion system (WECS) utilizing a permanent magnet induction generator (PMIG). Further, a syn- chronous generator (SG) is used with the diesel engine set for power generation. The mismatch between generated and consumed reactive power in the system causes voltage ﬂ uctuations, which will occur at generator terminals. These oscillations further causes reduction in the stability and quality of the power
Update : 2024-05-18 Size : 2063360 Publisher : Gomaa Haroun
【VHDL-FPGA-Verilog】 FPGA_AND_ASIC DL : 0: 首先要知道自己在干什么？数字电路(fpga/asic)设计就是逻辑电路的实现，这样子说太窄了，因为asic还有不少是模拟的，呵呵。我们这里只讨论数字电路设计。实际上就是如何把我们从课堂上学到的逻辑电路使用原理图(很少有人用这个拉)，或者硬件描述语言(Verilog/VHDL)来实现，或许你觉得这太简单了，其实再复杂的设计也就是用逻辑门电路搭起来的。你学习逻辑电路的时候或许会为卡拉图，触发器状态推倒公式而感到迷惑，但是其实有一点可以放心的是，实际设计中只要求你懂得接口时序和功能就可以了，用不着那么复杂得推倒公式，只要你能够用语言把逻辑关系表述清楚就可以了，具体这个逻辑关系采用什么门电路搭的，可以不关心，综合工具(synthesis tool)可以帮你处理。当然你要知道基本门电路的功能，比如D触发器，与门，非门，或门等的功能(不说多的，两输入的还是比较简单的)。-First of all to know what you are doing? Digital circuit (fpga/asic) design is the realization of the logic circuit, so that is too narrow, because there are a lot of asic simulation, huh, huh. We only discuss digital circuit design here. Is actually how we use the logic the classroom to use the schematic diagram (very few people use this pull), or hardware description language (Verilog/VHDL) to achieve, perhaps you think this is too simple, in fact, complex design That is, with the logic gate to build up. When you learn the logic of the circuit may be for the Karata, flip-flop state of the formula and feel confused, but in fact there is one thing can be assured that the actual design only requires you to understand the interface timing and function can be, and not so complicated Down the formula, as long as you can use the language to express the logical relationship can be clear, the specific logical relationship with what the door to take, you can not care, comprehensive tools (syn
Update : 2024-05-18 Size : 19456 Publisher : 吕攀攀
【OS program】 SYN DL : 0: 分布式网络同步算法，平均度对收敛速度的影响分析代码(distributed synchronization algorithm)
Update : 2024-05-18 Size : 56320 Publisher : 涂涂兽
【VHDL-FPGA-Verilog】 FIFO_RAM DL : 0: 同步FIFO_RAM的设计及其testbench(8 bit SYN FIFO module fifo_v(clk,rst,wen,ren,full,empty,data,q);)
Update : 2024-05-18 Size : 3072 Publisher : 炜仔mjw
【MPI】 gate_test DL : 0: 使用vivado hls 对GATE代码进行封装，主要调试stream接口(using vivado hls to archieve GATE syn, to debug the AXI4-stream interface)
Update : 2024-05-18 Size : 2184192 Publisher : beny270
【Linux-Unix】 b DL : 0: Linux SYN扫描器 by SIncoder(Linux SYN Port Scanner by SIncoder)
Update : 2024-05-18 Size : 5120 Publisher : CrackNote
【ELanguage】词法分析程序 DL : 0: 词法分析输入：所给文法的源程序字符串。输出：二元组（syn,token或sum）构成的序列。(lexical analysis Input: the source code string for the given grammar. Output: a sequence consisting of two tuples (syn, token, or sum).)
Update : 2024-05-18 Size : 1024 Publisher : 司空易
【Other】 Synchronous reset D DL : 0: Synchronous reset D- FF
Update : 2024-05-18 Size : 9216 Publisher : aswin
【ELanguage】编译原理词法分析器 DL : 0: 2.1 待分析的简单的词法（1）关键字： begin if then while do end 所有的关键字都是小写。（2）运算符和界符： = + - * / < <= <> > >= = ; ( ) # （3）其他单词是标识符（ID）和整型常数（SUM），通过以下正规式定义： ID = letter (letter | digit)* NUM = digit digit* （4）空格有空白、制表符和换行符组成。空格一般用来分隔ID、SUM、运算符、界符 1 ： 2 ：= 3 < 4 <> 5 <= 6 > 10 >= 11 = 13 ； 14 ( 15 ) 和关键字，词法分析阶段通常被忽略。 2.2 词法分析程序的功能：输入：所给文法的源程序字符串。输出：二元组（syn,token或sum）构成的序列。其中：syn为单词种别码； token为存放的单词自身字符串； sum为整型常数。例如：对源程序begin x:=9: if x>9 then x:=2*x+1/3; end #的源文件，经过词法分析后输出如下序列： (1,begin)(10,x)(18,:=)(11,9)(26,;)(2,if)……(The function of the lexical analysis program: Input: the source code string for the grammar. Output: a sequence of two tuples (syn, token, or sum). Among them: SYN is a word seed code; Token is the character string of the word that is stored. Sum is an integer constant. For example: begin x:=9: if x>9 then source program x:=2*x+1/3; end # source files, after lexical analysis and output sequences are as follows: (1, begin) (10, x) (18, = =) (11,9) (26,;) (2, if)...)
Update : 2024-05-18 Size : 3268608 Publisher : 帅帅的风

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