a rapidly 3des algorithm respectively vhcl Veriloge language and prepared very practical

Packet : 99274023fast_des.zip filelist
techpubs/appnotes/270/source/reference design inputs/readme.txt
techpubs/appnotes/270/source/reference design inputs/xapp270_verilog/Des/des.v
techpubs/appnotes/270/source/reference design inputs/xapp270_verilog/Des/des_const.v
techpubs/appnotes/270/source/reference design inputs/xapp270_verilog/Des/des_f.v
techpubs/appnotes/270/source/reference design inputs/xapp270_verilog/Des/des_key.v
techpubs/appnotes/270/source/reference design inputs/xapp270_verilog/Des/des_sbox.v
techpubs/appnotes/270/source/reference design inputs/xapp270_verilog/Testbench/des_testbench.vhd
techpubs/appnotes/270/source/reference design inputs/xapp270_verilog/Triple-DES/triple_des.v
techpubs/appnotes/270/source/reference design inputs/xapp270_vhdl/Des/des.vhd
techpubs/appnotes/270/source/reference design inputs/xapp270_vhdl/Des/des_const.vhd
techpubs/appnotes/270/source/reference design inputs/xapp270_vhdl/Des/des_f.vhd
techpubs/appnotes/270/source/reference design inputs/xapp270_vhdl/Des/des_key.vhd
techpubs/appnotes/270/source/reference design inputs/xapp270_vhdl/Des/des_sbox.vhd
techpubs/appnotes/270/source/reference design inputs/xapp270_vhdl/Testbench/des_testbench.vhd
techpubs/appnotes/270/source/reference design inputs/xapp270_vhdl/Triple-Des/triple_des.vhd

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