using Verilog This is a simple written by the processor, although with only five directives, through this example, to understand cpu architecture, how to develop processor, it would be very enlightening.

Packet : 61918sap1.rar filelist
sap1\sap1.adf
sap1\projlib.cfg
sap1\sap1.LIB
sap1\compile.cfg
sap1\bde.set
sap1\0.mgf
sap1\1.mgf
sap1\3.mgf
sap1\sap1.wsp
sap1\elaboration.log
sap1\compile\contents.lib~
sap1\compile\sap1.opt
sap1\compile\sap1.erf
sap1\compile\sap1.epr
sap1\compile\vcp.mod
sap1\compile\vcp.top
sap1\compile\mega.dag
sap1\compile\mega.elb
sap1\compile\mega.dbg
sap1\compile\mega.itf
sap1\compile\mega.asm
sap1\compile\mega.bin
sap1\compile\mega.off
sap1\compile\mega.mod
sap1\compile\sources.sth
sap1\compile\wave0.dat
sap1\compile\wave1.dat
sap1\compile\wave10.dat
sap1\compile\wave11.dat
sap1\compile\wave12.dat
sap1\compile\wave2.dat
sap1\compile\wave3.dat
sap1\compile\wave4.dat
sap1\compile\wave5.dat
sap1\compile\wave6.dat
sap1\compile\wave7.dat
sap1\compile\wave8.dat
sap1\compile\wave9.dat
sap1\compile
sap1\log\console.log
sap1\log\find.log
sap1\log\compile.log
sap1\log\simulation.log
sap1\log
sap1\src\prom.v
sap1\src\SAP_1.v
sap1\src\Waveform Editor 1.awf
sap1\src\TestBench\SAP_1_TB.v
sap1\src\TestBench\SAP_1_TB_runtest.do
sap1\src\TestBench\SAP_1_TB_settings.txt
sap1\src\TestBench
sap1\src
sap1

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．