This based on the DE2 board design with verliogHDL calendar, by the 1602 display and alarm, the whole point timekeeping functions, tested, absolutely correct, to use the above version quartus9.0 to open the programs

clk_1602
........\__Previews
........\..........\clk_1602.asm.rptPreview
........\clk_1602.asm.rpt
........\clk_1602.done
........\clk_1602.dpf
........\clk_1602.eda.rpt
........\clk_1602.fit.rpt
........\clk_1602.fit.summary
........\clk_1602.flow.rpt
........\clk_1602.map.rpt
........\clk_1602.map.summary
........\clk_1602.pin
........\clk_1602.pof
........\clk_1602.qpf
........\clk_1602.qsf
........\clk_1602.qws
........\clk_1602.sof
........\clk_1602.tan.rpt
........\clk_1602.tan.summary
........\clk_1602.v
........\clk_1602.v.bak
........\clock.v
........\clock.v.bak
........\db
........\..\clk_1602.ae.hdb
........\..\clk_1602.asm.qmsg
........\..\clk_1602.asm.rdb
........\..\clk_1602.cbx.xml
........\..\clk_1602.cmp.ecobp
........\..\clk_1602.cmp.kpt
........\..\clk_1602.cmp.rdb
........\..\clk_1602.cmp0.ddb
........\..\clk_1602.cmp_merge.kpt
........\..\clk_1602.db_info
........\..\clk_1602.eco.cdb
........\..\clk_1602.eda.qmsg
........\..\clk_1602.fit.qmsg
........\..\clk_1602.hier_info
........\..\clk_1602.hif
........\..\clk_1602.lpc.html
........\..\clk_1602.lpc.rdb
........\..\clk_1602.lpc.txt
........\..\clk_1602.map.bpm
........\..\clk_1602.map.cdb
........\..\clk_1602.map.ecobp
........\..\clk_1602.map.hdb
........\..\clk_1602.map.kpt
........\..\clk_1602.map.logdb
........\..\clk_1602.map.qmsg
........\..\clk_1602.map_bb.cdb
........\..\clk_1602.map_bb.hdb
........\..\clk_1602.map_bb.logdb
........\..\clk_1602.pre_map.cdb
........\..\clk_1602.pre_map.hdb
........\..\clk_1602.rpp.qmsg
........\..\clk_1602.rtlv.hdb
........\..\clk_1602.rtlv_sg.cdb
........\..\clk_1602.rtlv_sg_swap.cdb
........\..\clk_1602.sgate.rvd
........\..\clk_1602.sgate_sm.rvd
........\..\clk_1602.sgdiff.cdb
........\..\clk_1602.sgdiff.hdb
........\..\clk_1602.sld_design_entry.sci
........\..\clk_1602.sld_design_entry_dsc.sci
........\..\clk_1602.smart_action.txt
........\..\clk_1602.smp_dump.txt
........\..\clk_1602.syn_hier_info
........\..\clk_1602.tan.qmsg
........\..\clk_1602.tis_db_list.ddb
........\..\logic_util_heursitic.dat
........\..\prev_cmp_clk_1602.asm.qmsg
........\..\prev_cmp_clk_1602.eda.qmsg
........\..\prev_cmp_clk_1602.fit.qmsg
........\..\prev_cmp_clk_1602.map.qmsg
........\..\prev_cmp_clk_1602.qmsg
........\..\prev_cmp_clk_1602.tan.qmsg
........\display.v
........\display.v.bak
........\incremental_db
........\..............\README
........\..............\compiled_partitions
........\..............\...................\clk_1602.root_partition.cmp.cdb
........\..............\...................\clk_1602.root_partition.cmp.dfp
........\..............\...................\clk_1602.root_partition.cmp.hdb
........\..............\...................\clk_1602.root_partition.cmp.kpt
........\..............\...................\clk_1602.root_partition.cmp.logdb
........\..............\...................\clk_1602.root_partition.cmp.rcfdb
........\..............\...................\clk_1602.root_partition.cmp.re.rcfdb
........\..............\...................\clk_1602.root_partition.map.cdb
........\..............\...................\clk_1602.root_partition.map.dpi
........\..............\...................\clk_1602.root_partition.map.hdb
........\..............\...................\clk_1602.root_partition.map.kpt
........\keyscan.v
........\keyscan.v.bak
........\simulation
........\..........\modelsim
........\..........\........\clk_1602.sft
........\..........\........\clk_1602.vo
........\..........\........\clk_1602_modelsim.xrf

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