Realize large-scale use of FPGA design, may need to FPGA with multiple clocks to run multiple data path, the multi-clock FPGA design must be particularly careful to note the maximum clock rate, jitter, the largest number of clock, asynchronous clock design and clock/data relations. The design process the most important step is to determine how much it costs to different clocks, as well as how to carry out wiring

Packet : 89346490multi_clock_design_in_large_scale_fpga.rar filelist
大型设计中FPGA的多时钟设计策略.doc

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