PPM Verilog

PPM
...\ppm_receive
...\...........\BIT.bsf
...\...........\BIT.v
...\...........\BIT.v.bak
...\...........\EZUSB_FPGA连续传输加FIFO缓冲半空标志控制使用
...\...........\............................................\DataSource.bsf
...\...........\............................................\DataSource.vhd
...\...........\............................................\DataSource.vhd.bak
...\...........\............................................\EZUSBtransfer.bdf
...\...........\............................................\EZUSBtransfer.bsf
...\...........\............................................\FreQ.bsf
...\...........\............................................\FreQ.vhd
...\...........\............................................\FreQ.vhd.bak
...\...........\............................................\FreQ.vwf
...\...........\............................................\SlaveFIFO_FPGA.asm.rpt
...\...........\............................................\SlaveFIFO_FPGA.bdf
...\...........\............................................\SlaveFIFO_FPGA.cdf
...\...........\............................................\SlaveFIFO_FPGA.done
...\...........\............................................\SlaveFIFO_FPGA.dpf
...\...........\............................................\SlaveFIFO_FPGA.fit.rpt
...\...........\............................................\SlaveFIFO_FPGA.fit.smsg
...\...........\............................................\SlaveFIFO_FPGA.fit.summary
...\...........\............................................\SlaveFIFO_FPGA.flow.rpt
...\...........\............................................\SlaveFIFO_FPGA.jdi
...\...........\............................................\SlaveFIFO_FPGA.map.rpt
...\...........\............................................\SlaveFIFO_FPGA.map.summary
...\...........\............................................\SlaveFIFO_FPGA.pin
...\...........\............................................\SlaveFIFO_FPGA.pof
...\...........\............................................\SlaveFIFO_FPGA.qpf
...\...........\............................................\SlaveFIFO_FPGA.qsf
...\...........\............................................\SlaveFIFO_FPGA.qws
...\...........\............................................\SlaveFIFO_FPGA.sim.rpt
...\...........\............................................\SlaveFIFO_FPGA.sof
...\...........\............................................\SlaveFIFO_FPGA.tan.rpt
...\...........\............................................\SlaveFIFO_FPGA.tan.summary
...\...........\............................................\SlaveFIFO_FPGA.vwf
...\...........\............................................\SlaveFiFo_Write.bsf
...\...........\............................................\SlaveFiFo_Write.vhd
...\...........\............................................\SlaveFiFo_Write.vhd.bak
...\...........\............................................\SlaveFifo_Write.vwf
...\...........\............................................\db
...\...........\............................................\..\SlaveFIFO_FPGA.asm.qmsg
...\...........\............................................\..\SlaveFIFO_FPGA.cbx.xml
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.bpm
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.cdb
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.ecobp
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.hdb
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.kpt
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.logdb
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.rdb
...\...........\............................................\..\SlaveFIFO_FPGA.cmp.tdb
...\...........\............................................\..\SlaveFIFO_FPGA.cmp0.ddb
...\...........\............................................\..\SlaveFIFO_FPGA.cmp_merge.kpt
..

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