Give a 16 bits wide, depth of 10 asynchronous FIFO design, and requires giving empty or full instructions signal. Request using Verilog HDL language design, and the writing test, and simulation using Modelsim function, validate design is correct. 10 16 bits of data (THE WIDTH of THE FIFO, namely information in English often see THE WIDTH, it refers to a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit and so on. THE depth of FIFO: THE DEEPTH, it refers to THE FIFO can store many N bits of data (if THE WIDTH is N). If an 8-bit FIFO, if THE depth of 8, it can store 8 8 bits of data, THE depth of 12, 12 8 bits of data to be stored.)

fifo1\fifo1.cr.mti
.....\fifo1.mpf
.....\fifo1.v
.....\fifo1.v.bak
.....\fifo1_test.v
.....\fifo1_test.v.bak
.....\vsim.wlf
.....\work\@gray@counter_2\verilog.asm
.....\....\...............\_primary.dat
.....\....\...............\_primary.vhd
.....\....\fifo1\verilog.asm
.....\....\.....\_primary.dat
.....\....\.....\_primary.vhd
.....\....\....._test\verilog.asm
.....\....\..........\_primary.dat
.....\....\..........\_primary.vhd
.....\....\_info
.....\....\@gray@counter_2
.....\....\fifo1
.....\....\fifo1_test
.....\work
fifo1

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