this a verilog module.it have the fanction of selet the signal form two signals.

2_MUX_4_1_vt
............\quartus
............\.......\MUX_4_1.asm.rpt
............\.......\MUX_4_1.done
............\.......\MUX_4_1.eda.rpt
............\.......\MUX_4_1.fit.rpt
............\.......\MUX_4_1.fit.smsg
............\.......\MUX_4_1.fit.summary
............\.......\MUX_4_1.flow.rpt
............\.......\MUX_4_1.jdi
............\.......\MUX_4_1.map.rpt
............\.......\MUX_4_1.map.summary
............\.......\MUX_4_1.pin
............\.......\MUX_4_1.pof
............\.......\MUX_4_1.qpf
............\.......\MUX_4_1.qsf
............\.......\MUX_4_1.qws
............\.......\MUX_4_1.sta.rpt
............\.......\MUX_4_1.sta.summary
............\.......\MUX_4_1_nativelink_simulation.rpt
............\.......\db
............\.......\..\MUX_4_1.amm.cdb
............\.......\..\MUX_4_1.asm.qmsg
............\.......\..\MUX_4_1.asm.rdb
............\.......\..\MUX_4_1.asm_labs.ddb
............\.......\..\MUX_4_1.cbx.xml
............\.......\..\MUX_4_1.cmp.cdb
............\.......\..\MUX_4_1.cmp.hdb
............\.......\..\MUX_4_1.cmp.kpt
............\.......\..\MUX_4_1.cmp.logdb
............\.......\..\MUX_4_1.cmp.rdb
............\.......\..\MUX_4_1.cmp0.ddb
............\.......\..\MUX_4_1.db_info
............\.......\..\MUX_4_1.eda.qmsg
............\.......\..\MUX_4_1.fit.qmsg
............\.......\..\MUX_4_1.hier_info
............\.......\..\MUX_4_1.hif
............\.......\..\MUX_4_1.idb.cdb
............\.......\..\MUX_4_1.lpc.html
............\.......\..\MUX_4_1.lpc.rdb
............\.......\..\MUX_4_1.lpc.txt
............\.......\..\MUX_4_1.map.cdb
............\.......\..\MUX_4_1.map.hdb
............\.......\..\MUX_4_1.map.logdb
............\.......\..\MUX_4_1.map.qmsg
............\.......\..\MUX_4_1.map.rdb
............\.......\..\MUX_4_1.pre_map.cdb
............\.......\..\MUX_4_1.pre_map.hdb
............\.......\..\MUX_4_1.root_partition.map.reg_db.cdb
............\.......\..\MUX_4_1.routing.rdb
............\.......\..\MUX_4_1.rpp.qmsg
............\.......\..\MUX_4_1.rtlv.hdb
............\.......\..\MUX_4_1.rtlv_sg.cdb
............\.......\..\MUX_4_1.rtlv_sg_swap.cdb
............\.......\..\MUX_4_1.sgate.rvd
............\.......\..\MUX_4_1.sgate_sm.rvd
............\.......\..\MUX_4_1.sgdiff.cdb
............\.......\..\MUX_4_1.sgdiff.hdb
............\.......\..\MUX_4_1.sld_design_entry.sci
............\.......\..\MUX_4_1.sld_design_entry_dsc.sci
............\.......\..\MUX_4_1.smart_action.txt
............\.......\..\MUX_4_1.sta.qmsg
............\.......\..\MUX_4_1.sta.rdb
............\.......\..\MUX_4_1.sta_cmp.5_slow.tdb
............\.......\..\MUX_4_1.syn_hier_info
............\.......\..\MUX_4_1.tis_db_list.ddb
............\.......\..\logic_util_heursitic.dat
............\.......\..\prev_cmp_MUX_4_1.qmsg
............\.......\incremental_db
............\.......\..............\README
............\.......\..............\compiled_partitions
............\.......\..............\...................\MUX_4_1.db_info
............\.......\..............\...................\MUX_4_1.root_partition.map.kpt
............\.......\simulation
............\.......\..........\modelsim
............\.......\..........\........\MUX_4_1.sft
............\.......\..........\........\MUX_4_1.vo
............\.......\..........\........\MUX_4_1.vt
............\.......\..........\........\MUX_4_1.vt.bak
............\.......\..........\........\MUX_4_1.vt~
............\.......\..........\........\MUX_4_1_modelsim.xrf
............\.......\..........\........\MUX_4_1_run_msim_rtl_verilog.do
............\.......\..........\........\MUX_4_1_run_msim_rtl_verilog.do.bak
............\.......\..........\........\MUX_4_1_run_msim_rtl_verilog.do.bak1
............\.......\..........\........\MUX_4_1_run_msim_rtl_verilog.do.bak2
............\.......\..........\........\MUX_4_1_run_msim_rtl_verilog.do.bak3
............\.......\..........\........\MUX_4_1_v.sdo
............\.......\..........\........\modelsim.ini
............\.......\..........\........\msim_transcript
............\.......\..........\........\rtl_work
............\.......\..........\.

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