use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-

Packet : 165964cnt_24.rar filelist
CNT_24
CNT_24\cmp_state.ini
CNT_24\time.fit.rpt
CNT_24\time.fit.summary
CNT_24\time.flow.rpt
CNT_24\time.map.eqn
CNT_24\time.map.rpt
CNT_24\time.map.summary
CNT_24\time.pin
CNT_24\time.pof
CNT_24\time.qpf
CNT_24\time.qsf
CNT_24\time.qws
CNT_24\time.sim.rpt
CNT_24\time.sof
CNT_24\time.tan.rpt
CNT_24\time.tan.summary
CNT_24\time.vhd
CNT_24\time.vwf
CNT_24\sim.cfg
CNT_24\time.asm.rpt
CNT_24\time.done
CNT_24\time.fit.eqn
CNT_24\db
CNT_24\time.acf
CNT_24\time.hif

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