board ad7882 for altera

NiosCpu\altera_avalon_altpll_hw.tcl
.......\altera_avalon_clock_adapter.sdc
.......\altpll_0.v
.......\altpll_0.vo
.......\altpll_0_simgen_gate.xml
.......\BeforeI2C_assignment_defaults.qdf
.......\cpu.ocp
.......\cpu.sdc
.......\cpu.v
.......\cpu_jtag_debug_module_sysclk.v
.......\cpu_jtag_debug_module_tck.v
.......\cpu_jtag_debug_module_wrapper.v
.......\cpu_oci_test_bench.v
.......\cpu_ociram_default_contents.mif
.......\cpu_rf_ram_a.mif
.......\cpu_rf_ram_b.mif
.......\cpu_test_bench.v
.......\ctrl.v
.......\epcs_flash_controller.v
.......\epcs_flash_controller_boot_rom.hex
.......\epcs_flash_controller_boot_rom_synth.hex
.......\fpga.asm.rpt
.......\fpga.cbx.xml
.......\fpga.cdf
.......\fpga.done
.......\fpga.eda.rpt
.......\fpga.fit.rpt
.......\fpga.fit.summary
.......\fpga.flow.rpt
.......\fpga.jdi
.......\fpga.map.rpt
.......\fpga.map.smsg
.......\fpga.map.summary
.......\fpga.pin
.......\fpga.qpf
.......\fpga.qsf
.......\fpga.sdc
.......\fpga.sof
.......\fpga.srf
.......\fpga.sta.rpt
.......\fpga.sta.summary
.......\fpga.v
.......\fpga_assignment_defaults.qdf
.......\fpga_description.txt
.......\fpga_nativelink_simulation.rpt
.......\gpio.v
.......\ip
.......\..\AD7982
.......\..\......\Docs
.......\..\......\....\AD7982.pdf
.......\..\......\hdl
.......\..\......\...\src
.......\..\......\...\...\AD7982.v
.......\..\......\...\...\AD7982_sw.tcl
.......\..\......\...\...\ad7982top.v
.......\..\......\...\...\ad7982top_hw.tcl
.......\..\......\...\...\HAL
.......\..\......\...\...\...\inc
.......\..\......\...\...\...\...\ad7982.h
.......\..\......\...\...\...\src
.......\..\......\...\...\...\...\ad7982.c
.......\..\......\...\...\inc
.......\..\......\...\...\...\ad7982_regs.h
.......\..\......\...\...\write_master.v
.......\..\......\...\tb
.......\..\......\...\..\AD7982.vt
.......\jtag_uart.v
.......\led.v
.......\main_pll.v
.......\main_pll.vo
.......\master_0.v
.......\meminit.qip
.......\meminit.spd
.......\onchip_ram.hex
.......\onchip_ram.v
.......\PLLJ_PLLSPE_INFO.txt
.......\prmtvs_b.vhd
.......\prmtvs_p.vhd
.......\SDP1_bemicro2.cof
.......\SDP1_bemicro2.jic
.......\SDP1_bemicro2.map
.......\sopc_add_qip_file.tcl
.......\sysid.v
.......\timer.v
.......\timing_b.vhd
.......\timing_p.vhd
.......\uC.bsf
.......\uC.html
.......\uC.ptf
.......\uC.ptf.8.0
.......\uC.ptf.pre_generation_ptf
.......\uC.qip
.......\uC.qsys
.......\uC.sopcinfo
.......\uC.v
.......\uC_clock_0.v
.......\uC_clock_1.v
.......\uC_clock_2.v
.......\uC_clock_3.v
.......\uC_clock_4.v

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