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For FPGA state machine design experience
For FPGA state machine design is divided into two categories, divided output mealy state machine and Moore state machine, mealy state machine has not only the current state of the input current, whereas the output Moore state machine only with the current status. For the description of the state machine must first know the input, output, current state, the basic definition of a state.
For non-state machine design, the first to have an initial state, generically named IDLE, its status is generally set at the time of the reset signal comes.
Sensitive to the clock signal at its clock period as a maximum of the total circulating state, a clock signal under the most state instruction, a timing chart for describing general for non-sensitive clock signal, for each current working Analyzing the state, generally used to describe control. For the description of the timing diagram, which is similar to the control process, as compared to the C language