DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M

Packet : 111186776ref-sdr-sdram-vhdl.zip filelist
CVS/
doc/
doc/CVS/
readme_sdr_sdram.txt
sdr_sdram.pdf
simulation/
simulation/CVS/
simulation/sdr_sdram_tb.vhd
source/
source/Command.vhd
source/control_interface.vhd
source/CVS/
source/pll1.vhd
source/sdr_data_path.vhd
source/sdr_sdram.vhd

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