full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.

model\mt46v4m16.vhd
.....\mti_pkg.vhd
route\ddr_sdram.csf
.....\ddr_sdram.esf
.....\ddr_sdram.psf
.....\ddr_sdram.quartus
.....\ddr_sdram.vqm
.....\pll1.vhd
simulation\APEX20KE_MF.VHD
..........\ddr_sdram_tb.vhd
..........\modelsim.ini
..........\mti_pkg.bak
..........\readme.txt
..........\wave.do
..........\.ork\altcam\behave.psm
..........\....\....lklock\behavior.dat
..........\....\..........\behavior.psm
..........\....\...lvds_rx\behavior.psm
..........\....\........tx\behavior.psm
..........\....\control_interface\rtl.dat
..........\....\.................\rtl.psm
..........\....\ddr_command\rtl.dat
..........\....\...........\rtl.psm
..........\....\...........\_primary.dat
..........\....\......ntrol_interface\rtl.dat
..........\....\.....................\rtl.psm
..........\....\.....................\_primary.dat
..........\....\....data_path\rtl.dat
..........\....\.............\rtl.psm
..........\....\.............\_primary.dat
..........\....\....sdram\rtl.dat
..........\....\.........\rtl.psm
..........\....\.........\_primary.dat
..........\....\........._tb\rtl.dat
..........\....\............\rtl.psm
..........\....\io_utils\body.psm
..........\....\lpm_components\body.dat
..........\....\..............\body.psm
..........\....\..............\_primary.dat
..........\....\..............\_vhdl.psm
..........\....\mt46v4m16\behave.dat
..........\....\.........\behave.psm
..........\....\.........\_primary.dat
..........\....\..i_pkg\body.dat
..........\....\.......\body.psm
..........\....\.......\_primary.dat
..........\....\.......\_vhdl.psm
..........\....\pll1\syn.dat
..........\....\....\syn.psm
..........\....\....\_primary.dat
..........\....\std_logic_arith\body.psm
..........\....\_info
.ource\ddr_command.vhd
......\ddr_control_interface.vhd
......\ddr_data_path.vhd
......\ddr_sdram.vhd
.ynthesis\synplicity\ddr_sdram.prj
.........\..........\rev_1\ddr_sdram.srm
.........\..........\.....\ddr_sdram.srr
.........\..........\.....\ddr_sdram.srs
.........\..........\.....\ddr_sdram.tcl
.........\..........\.....\ddr_sdram.tlg
.........\..........\.....\ddr_sdram.vqm
.........\..........\.....\ddr_sdram.xrf
.........\..........\.....\ddr_sdram_rm.tcl
readme.txt
simulation\work\altcam
..........\....\altclklock
..........\....\altlvds_rx
..........\....\altlvds_tx
..........\....\control_interface
..........\....\ddr_command
..........\....\ddr_control_interface
..........\....\ddr_data_path
..........\....\ddr_sdram
..........\....\ddr_sdram_tb
..........\....\io_utils
..........\....\lpm_components
..........\....\mt46v4m16
..........\....\mti_pkg
..........\....\pll1
..........\....\std_logic_arith
.ynthesis\synplicity\rev_1
.imulation\work
.ynthesis\synplicity
model
route
simulation
source
synthesis

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