Introduction - If you have any usage issues, please Google them yourself
digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Packet : 31767651数字锁相环设计源程序.rar filelist
pll\aa.gdf
pll\edge.acf
pll\edge.cnf
pll\edge.fit
pll\edge.gdf
pll\edge.hex
pll\edge.hif
pll\edge.mmf
pll\edge.ndb
pll\edge.pin
pll\edge.pof
pll\edge.rpt
pll\edge.scf
pll\edge.snf
pll\edge.sof
pll\edge.ttf
pll\inst1.gdf
pll\mealy1.acf
pll\mealy1.cnf
pll\mealy1.fit
pll\mealy1.gdf
pll\mealy1.hex
pll\mealy1.hif
pll\mealy1.mmf
pll\mealy1.ndb
pll\mealy1.pin
pll\mealy1.pof
pll\mealy1.rpt
pll\mealy1.scf
pll\mealy1.snf
pll\mealy1.sof
pll\mealy1.ttf
pll\pll(1).cnf
pll\pll(2).cnf
pll\pll(3).cnf
pll\pll(4).cnf
pll\pll(5).cnf
pll\pll.acf
pll\pll.cnf
pll\pll.fit
pll\pll.gdf
pll\pll.hif
pll\pll.jam
pll\pll.jbc
pll\pll.mmf
pll\pll.ndb
pll\pll.pin
pll\pll.pof
pll\pll.rpt
pll\pll.scf
pll\pll.snf
pll\pll1(1).cnf
pll\pll1(2).cnf
pll\pll1(3).cnf
pll\pll1(4).cnf
pll\pll1.acf
pll\pll1.cnf
pll\pll1.fit
pll\pll1.gdf
pll\pll1.hif
pll\pll1.jam
pll\pll1.jbc
pll\pll1.mmf
pll\pll1.ndb
pll\pll1.pin
pll\pll1.pof
pll\pll1.rpt
pll\pll1.snf
pll
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