The use of Verilog language, the design of crossovers, it is a good reference

Packet : 31767637fenpin.rar filelist
fenpin\counter11.v
fenpin\couter10.v
fenpin\enable.v
fenpin\fen_pin_10_1.bdf
fenpin\fen_pin_10_1.qpf
fenpin\fen_pin_10_1.qsf
fenpin\db\wed.zsf
fenpin\db\fen_pin_10_1.db_info
fenpin\db\fen_pin_10_1.fit.qmsg
fenpin\db\fen_pin_10_1.(0).cnf.cdb
fenpin\db\fen_pin_10_1.tan.qmsg
fenpin\db\fen_pin_10_1.eda.qmsg
fenpin\db\fen_pin_10_1.rtlv.hdb
fenpin\db\fen_pin_10_1.(0).cnf.hdb
fenpin\db\fen_pin_10_1.rtlv_sg.cdb
fenpin\db\fen_pin_10_1.pre_map.hdb
fenpin\db\fen_pin_10_1.fnsim.qmsg
fenpin\db\fen_pin_10_1.sim.qmsg
fenpin\db\fen_pin_10_1.fnsim.cdb
fenpin\db\fen_pin_10_1.pre_map.cdb
fenpin\db\fen_pin_10_1.eco.cdb
fenpin\db\fen_pin_10_1.map.qmsg
fenpin\db\fen_pin_10_1.sld_design_entry_dsc.sci
fenpin\db\fen_pin_10_1.rtlv_sg_swap.cdb
fenpin\db\fen_pin_10_1.sim.hdb
fenpin\db\fen_pin_10_1.cbx.xml
fenpin\db\fen_pin_10_1.hif
fenpin\db\fen_pin_10_1.eds_overflow
fenpin\db\fen_pin_10_1.map.logdb
fenpin\db\fen_pin_10_1.sim.vwf
fenpin\db\fen_pin_10_1.map.cdb
fenpin\db\fen_pin_10_1.sim.rdb
fenpin\db\fen_pin_10_1.(1).cnf.cdb
fenpin\db\fen_pin_10_1.cmp.cdb
fenpin\db\fen_pin_10_1.(1).cnf.hdb
fenpin\db\fen_pin_10_1.sgdiff.cdb
fenpin\db\fen_pin_10_1.(2).cnf.cdb
fenpin\db\fen_pin_10_1.sgdiff.hdb
fenpin\db\fen_pin_10_1.(2).cnf.hdb
fenpin\db\fen_pin_10_1.map.hdb
fenpin\db\fen_pin_10_1.(3).cnf.cdb
fenpin\db\fen_pin_10_1.asm.qmsg
fenpin\db\fen_pin_10_1.(3).cnf.hdb
fenpin\db\fen_pin_10_1.hier_info
fenpin\db\fen_pin_10_1.cmp.logdb
fenpin\db\fen_pin_10_1.cmp2.ddb
fenpin\db\fen_pin_10_1.cmp.rdb
fenpin\db\fen_pin_10_1.cmp.hdb
fenpin\db\fen_pin_10_1.cmp.tdb
fenpin\db\fen_pin_10_1.asm_labs.ddb
fenpin\db\fen_pin_10_1.psp
fenpin\db\fen_pin_10_1.dbp
fenpin\db\fen_pin_10_1.fnsim.hdb
fenpin\db\fen_pin_10_1.cmp0.ddb
fenpin\db\fen_pin_10_1.signalprobe.cdb
fenpin\db\fen_pin_10_1.sld_design_entry.sci
fenpin\db\fen_pin_10_1.syn_hier_info
fenpin\db\fen_pin_10_1.cmp.kpt
fenpin\db
fenpin\counter11.bsf
fenpin\fen_pin_10_1.done
fenpin\counter10.bsf
fenpin\enable.bsf
fenpin\fen_pin_10_1.map.rpt
fenpin\fen_pin_10_1.flow.rpt
fenpin\fen_pin_10_1.map.summary
fenpin\fen_pin_10_1.pin
fenpin\fen_pin_10_1.fit.rpt
fenpin\fen_pin_10_1.fit.smsg
fenpin\fen_pin_10_1.fit.summary
fenpin\fen_pin_10_1.sof
fenpin\fen_pin_10_1.pof
fenpin\fen_pin_10_1.asm.rpt
fenpin\fen_pin_10_1.tan.summary
fenpin\fen_pin_10_1.tan.rpt
fenpin\simulation\modelsim\fen_pin_10_1_modelsim.xrf
fenpin\simulation\modelsim\fen_pin_10_1.vo
fenpin\simulation\modelsim\fen_pin_10_1_v.sdo
fenpin\simulation\modelsim
fenpin\simulation\fen_pin_10_1.vwf
fenpin\simulation
fenpin\fen_pin_10_1.eda.rpt
fenpin\fen_pin_10_1.sim.rpt
fenpin\fen_pin_10_1.qws
fenpin

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