The upper machine of virtual logic analyzer, logic analyzers trigger word of operating rules are soft

4CursorListView.cpp
8ConfigDlg.h
CursorView.cpp
CursorView.h
DisplayData.cpp
DisplayData.h
Globals.h
image
.....\Signal.bmp
.....\Signal2.bmp
KConfigDlg.cpp
MainFrm.cpp
MainFrm.h
ReadMe.txt
resource.h
serialport.cpp
serialport.h
SerialPortThread.cpp
SerialPortThread.h
SignalsTreeView.cpp
SignalsTreeView.h
StdAfx.cpp
StdAfx.h
Virtual Logical Analyser.aps
Virtual Logical Analyser.clw
Virtual Logical Analyser.cpp
Virtual Logical Analyser.dsp
Virtual Logical Analyser.dsw
Virtual Logical Analyser.h
Virtual Logical Analyser.ncb
Virtual Logical Analyser.opt
Virtual Logical Analyser.plg
Virtual Logical Analyser.rc
Virtual Logical Analyser.reg
Virtual Logical Analyser.vpj
Virtual Logical Analyser.vpw
Virtual Logical Analyser.vpwhist
Virtual Logical Analyser.vtg
Virtual Logical AnalyserDoc.cpp
Virtual Logical AnalyserDoc.h
Virtual Logical AnalyserView.cpp
Virtual Logical AnalyserView.h
yCursorListView.h

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