The design of the SPI module based on FPGA, the main device is stm32

06_MCU2FPGA_SPI_Test\dev\db\MCU2FPGA_SPI_Test.db_info
....................\...\..\MCU2FPGA_SPI_Test.ipinfo
....................\...\..\MCU2FPGA_SPI_Test.sld_design_entry.sci
....................\...\MCU2FPGA_SPI_Test.qpf
....................\...\MCU2FPGA_SPI_Test.qsf
....................\...\MCU2FPGA_SPI_Test.qws
....................\...\MCU2FPGA_SPI_Test.tcl
....................\...\output_files\MCU2FPGA_SPI_Test.asm.rpt
....................\...\............\MCU2FPGA_SPI_Test.done
....................\...\............\MCU2FPGA_SPI_Test.fit.rpt
....................\...\............\MCU2FPGA_SPI_Test.fit.smsg
....................\...\............\MCU2FPGA_SPI_Test.fit.summary
....................\...\............\MCU2FPGA_SPI_Test.flow.rpt
....................\...\............\MCU2FPGA_SPI_Test.jdi
....................\...\............\MCU2FPGA_SPI_Test.map.rpt
....................\...\............\MCU2FPGA_SPI_Test.map.smsg
....................\...\............\MCU2FPGA_SPI_Test.map.summary
....................\...\............\MCU2FPGA_SPI_Test.pin
....................\...\............\MCU2FPGA_SPI_Test.sof
....................\...\............\MCU2FPGA_SPI_Test.sta.rpt
....................\...\............\MCU2FPGA_SPI_Test.sta.summary
....................\...\PLLJ_PLLSPE_INFO.txt
....................\...\sys_pll.qip
....................\...\VIP_System.sdc
....................\...\VIP_System.sdc.bak
....................\.oc\SPI_Code4FPGA\Project\Debug\Exe\SPI_Code4FPGA.hex
....................\...\.............\.......\.....\...\SPI_Code4FPGA.out
....................\...\.............\.......\.....\Obj\main.o
....................\...\.............\.......\.....\...\SPI_Code4FPGA.pbd
....................\...\.............\.......\settings\SPI_Code4FPGA.cspy.bat
....................\...\.............\.......\........\SPI_Code4FPGA.dbgdt
....................\...\.............\.......\........\SPI_Code4FPGA.dni
....................\...\.............\.......\........\SPI_Code4FPGA.wsdt
....................\...\.............\.......\SPI_Code4FPGA.dep
....................\...\.............\.......\SPI_Code4FPGA.ewd
....................\...\.............\.......\SPI_Code4FPGA.ewp
....................\...\.............\.......\SPI_Code4FPGA.eww
....................\...\.............\User\main.c
....................\sim\MCU2FPGA_SPI_TB\MCU2FPGA_SPI_TB.cr.mti
....................\...\...............\MCU2FPGA_SPI_TB.mpf
....................\...\...............\MCU2FPGA_SPI_TB.v
....................\...\...............\spi_index\spi_receiver.v
....................\...\...............\.........\spi_transfer.v
....................\...\...............\transcript
....................\...\...............\vsim.wlf
....................\...\...............\wave.do
....................\...\...............\.ork\@m@c@u2@f@p@g@a_@s@p@i_@t@b\verilog.prw
....................\...\...............\....\...........................\verilog.psm
....................\...\...............\....\...........................\_primary.dat
....................\...\...............\....\...........................\_primary.dbs
....................\...\...............\....\...........................\_primary.vhd
....................\...\...............\....\spi_receiver\verilog.prw
....................\...\...............\....\............\verilog.psm
....................\...\...............\....\............\_primary.dat
....................\...\...............\....\............\_primary.dbs
....................\...\...............\....\............\_primary.vhd
....................\...\...............\....\....transfer\verilog.prw
....................\...\...............\....\............\verilog.psm
....................\...\...............\....\............\_primary.dat
....................\...\...............\....\............\_primary.dbs
....................\...\...............\....\............\_primary.vhd
....................\...\...............\....\_info
....................\...\...............\....\_vmake
....................\...\...............\_

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