VHDL realize many times frequency multiplier circuit dual frequency multiplier = 2 (n+ 1)

Packet : 11912908test.rar filelist
test\cmp_state.ini
test\db\add_sub_0sh.tdf
test\db\add_sub_vrh.tdf
test\db\test1.(0).cnf.cdb
test\db\test1.(0).cnf.hdb
test\db\test1.asm.qmsg
test\db\test1.cbx.xml
test\db\test1.cmp.cdb
test\db\test1.cmp.hdb
test\db\test1.cmp.logdb
test\db\test1.cmp.rdb
test\db\test1.cmp.tdb
test\db\test1.cmp0.ddb
test\db\test1.db_info
test\db\test1.eco.cdb
test\db\test1.eds_overflow
test\db\test1.fit.qmsg
test\db\test1.fnsim.cdb
test\db\test1.fnsim.hdb
test\db\test1.hier_info
test\db\test1.hif
test\db\test1.map.cdb
test\db\test1.map.hdb
test\db\test1.map.logdb
test\db\test1.map.qmsg
test\db\test1.pre_map.cdb
test\db\test1.pre_map.hdb
test\db\test1.psp
test\db\test1.rtlv.hdb
test\db\test1.rtlv_sg.cdb
test\db\test1.rtlv_sg_swap.cdb
test\db\test1.sgdiff.cdb
test\db\test1.sgdiff.hdb
test\db\test1.signalprobe.cdb
test\db\test1.sim.hdb
test\db\test1.sim.qmsg
test\db\test1.sim.rdb
test\db\test1.sim.vwf
test\db\test1.sld_design_entry.sci
test\db\test1.sld_design_entry_dsc.sci
test\db\test1.syn_hier_info
test\db\test1.tan.qmsg
test\db\test1_cmp.qrpt
test\db\test1_sim.qrpt
test\talkback\test1.asm.talkback.xml
test\talkback\test1.fit.talkback.xml
test\talkback\test1.map.talkback.xml
test\talkback\test1.sim.talkback.xml
test\talkback\test1.tan.talkback.xml
test\test.qpf
test\test.qws
test\test1.asm.rpt
test\test1.done
test\test1.fit.eqn
test\test1.fit.rpt
test\test1.fit.summary
test\test1.flow.rpt
test\test1.inc
test\test1.map.eqn
test\test1.map.rpt
test\test1.map.summary
test\test1.pin
test\test1.qsf
test\test1.sim.rpt
test\test1.tan.rpt
test\test1.tan.summary
test\test1.v
test\test1.vhd
test\test1.vwf
test\Waveform1.vwf
test\偶数倍频.txt
test\db
test\talkback
test

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