Using FPGA to achieve the ADC sampler, using VHDL prepared 8-channel analog signal address, 8-bit data output

Packet : 79419134adc1.rar filelist
ADC1
ADC1\ADCINT.qpf
ADC1\ADCINT.qsf
ADC1\db
ADC1\db\ADCINT.db_info
ADC1\db\ADCINT.eco.cdb
ADC1\db\ADCINT.rpp.qmsg
ADC1\db\ADCINT.map.qmsg
ADC1\db\ADCINT.cmp.tdb
ADC1\db\ADCINT.cmp.qrpt
ADC1\db\ADCINT.cbx.xml
ADC1\db\ADCINT.hif
ADC1\db\ADCINT.(0).cnf.cdb
ADC1\db\ADCINT.(0).cnf.hdb
ADC1\db\ADCINT.hier_info
ADC1\db\ADCINT.rtlv_sg.cdb
ADC1\db\ADCINT.rtlv.hdb
ADC1\db\ADCINT.cmp0.ddb
ADC1\db\ADCINT.rtlv_sg_swap.cdb
ADC1\db\ADCINT.pre_map.hdb
ADC1\db\ADCINT.pre_map.cdb
ADC1\db\ADCINT.psp
ADC1\db\ADCINT.dbp
ADC1\db\ADCINT.smp_dump.txt
ADC1\db\ADCINT.sgdiff.cdb
ADC1\db\ADCINT.sgdiff.hdb
ADC1\db\ADCINT.sld_design_entry_dsc.sci
ADC1\db\ADCINT.syn_hier_info
ADC1\db\ADCINT.map.cdb
ADC1\db\ADCINT.map.hdb
ADC1\db\ADCINT.cmp.cdb
ADC1\db\ADCINT.fit.qmsg
ADC1\db\ADCINT.signalprobe.cdb
ADC1\db\ADCINT.cmp.hdb
ADC1\db\ADCINT.cmp.rdb
ADC1\db\ADCINT.sgate.rvd
ADC1\db\ADCINT.sgate_sm.rvd
ADC1\db\ADCINT.sld_design_entry.sci
ADC1\db\ADCINT.asm.qmsg
ADC1\db\ADCINT.tan.qmsg
ADC1\ADCINT.VHD
ADC1\ADCINT.map.eqn
ADC1\ADCINT.map.rpt
ADC1\ADCINT.flow.rpt
ADC1\ADCINT.map.summary
ADC1\ADCINT.fit.eqn
ADC1\ADCINT.pin
ADC1\ADCINT.fit.rpt
ADC1\ADCINT.fit.summary
ADC1\ADCINT.sof
ADC1\ADCINT.pof
ADC1\ADCINT.asm.rpt
ADC1\ADCINT.tan.summary
ADC1\ADCINT.tan.rpt
ADC1\ADCINT.done
ADC1\ADCINT.qws

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