The Verilog program runs on the FPGA to control the ADC. The control module provides the clock and control signals to complete the quantization and coding of analog signals.

Packet : 67506278sample8.rar filelist
sample\ADCINT.VHD
sample\db\altsyncram_5hb2.tdf
sample\db\cmpr_5mh.tdf
sample\db\cntr_09b.tdf
sample\db\cntr_afd.tdf
sample\db\cntr_kkb.tdf
sample\db\cntr_lbc.tdf
sample\db\cntr_ria.tdf
sample\db\decode_9ie.tdf
sample\db\sample.(0).cnf.cdb
sample\db\sample.(0).cnf.hdb
sample\db\sample.(1).cnf.cdb
sample\db\sample.(1).cnf.hdb
sample\db\sample.(10).cnf.cdb
sample\db\sample.(10).cnf.hdb
sample\db\sample.(11).cnf.cdb
sample\db\sample.(11).cnf.hdb
sample\db\sample.(12).cnf.cdb
sample\db\sample.(12).cnf.hdb
sample\db\sample.(13).cnf.cdb
sample\db\sample.(13).cnf.hdb
sample\db\sample.(14).cnf.cdb
sample\db\sample.(14).cnf.hdb
sample\db\sample.(15).cnf.cdb
sample\db\sample.(15).cnf.hdb
sample\db\sample.(16).cnf.cdb
sample\db\sample.(16).cnf.hdb
sample\db\sample.(17).cnf.cdb
sample\db\sample.(17).cnf.hdb
sample\db\sample.(18).cnf.cdb
sample\db\sample.(18).cnf.hdb
sample\db\sample.(19).cnf.cdb
sample\db\sample.(19).cnf.hdb
sample\db\sample.(2).cnf.cdb
sample\db\sample.(2).cnf.hdb
sample\db\sample.(20).cnf.cdb
sample\db\sample.(20).cnf.hdb
sample\db\sample.(21).cnf.cdb
sample\db\sample.(21).cnf.hdb
sample\db\sample.(22).cnf.cdb
sample\db\sample.(22).cnf.hdb
sample\db\sample.(23).cnf.cdb
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sample\db\sample.(24).cnf.cdb
sample\db\sample.(24).cnf.hdb
sample\db\sample.(25).cnf.cdb
sample\db\sample.(25).cnf.hdb
sample\db\sample.(26).cnf.cdb
sample\db\sample.(26).cnf.hdb
sample\db\sample.(27).cnf.cdb
sample\db\sample.(27).cnf.hdb
sample\db\sample.(28).cnf.cdb
sample\db\sample.(28).cnf.hdb
sample\db\sample.(29).cnf.cdb
sample\db\sample.(29).cnf.hdb
sample\db\sample.(3).cnf.cdb
sample\db\sample.(3).cnf.hdb
sample\db\sample.(30).cnf.cdb
sample\db\sample.(30).cnf.hdb
sample\db\sample.(31).cnf.cdb
sample\db\sample.(31).cnf.hdb
sample\db\sample.(32).cnf.cdb
sample\db\sample.(32).cnf.hdb
sample\db\sample.(33).cnf.cdb
sample\db\sample.(33).cnf.hdb
sample\db\sample.(34).cnf.cdb
sample\db\sample.(34).cnf.hdb
sample\db\sample.(35).cnf.cdb
sample\db\sample.(35).cnf.hdb
sample\db\sample.(36).cnf.cdb
sample\db\sample.(36).cnf.hdb
sample\db\sample.(37).cnf.cdb
sample\db\sample.(37).cnf.hdb
sample\db\sample.(38).cnf.cdb
sample\db\sample.(38).cnf.hdb
sample\db\sample.(39).cnf.cdb
sample\db\sample.(39).cnf.hdb
sample\db\sample.(4).cnf.cdb
sample\db\sample.(4).cnf.hdb
sample\db\sample.(40).cnf.cdb
sample\db\sample.(40).cnf.hdb
sample\db\sample.(41).cnf.cdb
sample\db\sample.(41).cnf.hdb
sample\db\sample.(5).cnf.cdb
sample\db\sample.(5).cnf.hdb
sample\db\sample.(6).cnf.cdb
sample\db\sample.(6).cnf.hdb
sample\db\sample.(7).cnf.cdb
sample\db\sample.(7).cnf.hdb
sample\db\sample.(8).cnf.cdb
sample\db\sample.(8).cnf.hdb
sample\db\sample.(9).cnf.cdb
sample\db\sample.(9).cnf.hdb
sample\db\sample.asm.qmsg
sample\db\sample.cbx.xml
sample\db\sample.cmp.cdb
sample\db\sample.cmp.hdb
sample\db\sample.cmp.qrpt
sample\db\sample.cmp.rdb
sample\db\sample.cmp.tdb
sample\db\sample.cmp0.ddb
sample\db\sample.dbp
sample\db\sample.db_info
sample\db\sample.eco.cdb
sample\db\sample.eds_overflow
sample\db\sample.fit.qmsg
sample\db\sample.hier_info
sample\db\sample.hif
sample\db\sample.map.cdb
sample\db\sample.map.hdb
sample\db\sample.map.qmsg
sample\db\sample.pre_map.cdb
sample\db\sample.pre_map.hdb
sample\db\sample.psp
sample\db\sample.rpp.qmsg
sample\db\sample.rtlv.hdb
sample\db\sample.rtlv_sg.cdb
sample\db\sample.rtlv_sg_swap.cdb
sample\db\sample.sgate.rvd
sample\db\sample.sgate_sm.rvd
sample\db\sample.sgdiff.cdb
sample\db\sample.sgdiff.hdb
sample\db\sample.signalprobe.cdb
sample\db\sample.sim.hdb
sample\db\sample.sim.qmsg
sample\db\sample.sim.qrpt
sample\db\sample.sim.rdb
sample\db\sample.sim.vwf
sample\db\sample.sld_design_entry.sci
sample\db\sample.sld_design_entry_dsc.sci
sample\db\sample.smp_dump.txt
sample\db\sample.syn_hier_info
sample\db\sample.tan.qmsg
sample\db
sample\sample.asm.rpt
sample\sample.bsf
sample\sample.cdf
sample\sample.done
sample\sample.fit.eqn
sample\sample.fit.rpt
sample\sample.fit.summary
sample\sample.flow.rpt
sample\sample.map.eqn
sample\sample.map.rpt
sample\sample.map.summary
sample\sample.pin
sample\sample.pof
sample\sample.qpf
sample\sample.qsf
sample\sample.qws
sample\sample.sim.rpt
sample\sample.sof
sample\sample.tan.rpt
sample\sample.tan.summary
sample\sample.v
sample\sample.vwf
sample\stp1.stp
sample

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