A clock used to write VHDL code, the upload is project-type increase in the experimental plate is passed, for your reference

Packet : 49636980clock.rar filelist
clock\chip_editor.acv
clock\clock.qpf
clock\clock.qsf
clock\clock.pin
clock\decoder7s.vhd
clock\division.vhd
clock\clock.map.rpt
clock\clock.flow.rpt
clock\reg.vhd
clock\clock.cdf
clock\clock.qws
clock\cmp_state.ini
clock\clock_assignment_defaults.qdf
clock\clock.map.summary
clock\count24.vhd
clock\clock.sof
clock\count12.vhd
clock\timingrun.vhd
clock\clock.map.eqn
clock\clock.fit.eqn
clock\clock.fit.rpt
clock\clock.fit.summary
clock\clock.pof
clock\clock.asm.rpt
clock\clock.tan.summary
clock\clock.dpf
clock\count6.vhd
clock\count10.vhd
clock\scan.vhd
clock\clock.tan.rpt
clock\clock.done
clock\clock.vhd
clock\timing.vhd
clock\db\clock.fit.qmsg
clock\db\clock.cmp.rdb
clock\db\clock.sld_design_entry.sci
clock\db\clock.rtlv_sg_swap.cdb
clock\db\clock.map.qmsg
clock\db\clock.eco.cdb
clock\db\clock.pre_map.hdb
clock\db\clock.pre_map.cdb
clock\db\clock.sgdiff.cdb
clock\db\clock.sgdiff.hdb
clock\db\clock.(0).cnf.cdb
clock\db\clock.rtlv_sg.cdb
clock\db\clock.rtlv.hdb
clock\db\clock.(0).cnf.hdb
clock\db\clock.sld_design_entry_dsc.sci
clock\db\clock.asm.qmsg
clock\db\clock.map.cdb
clock\db\clock.map.hdb
clock\db\clock.cmp.cdb
clock\db\clock.cmp.hdb
clock\db\clock.tan.qmsg
clock\db\clock.cmp0.ddb
clock\db\clock.cmp.tdb
clock\db\clock_hier_info
clock\db\clock_syn_hier_info
clock\db\clock_cmp.qrpt
clock\db\add_sub_soh.tdf
clock\db\clock(0).cnf.cdb
clock\db\clock(0).cnf.hdb
clock\db\clock.db_info
clock\db\clock.cmp.qrpt
clock\db\clock.cbx.xml
clock\db\clock.hif
clock\db\clock.hier_info
clock\db\clock.psp
clock\db\clock.dbp
clock\db\clock.syn_hier_info
clock\serv_req_info.txt
clock\db
clock

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