Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads Other resource
  • Category : Other resource
  • Tags :
  • Update : 2008-10-13
  • Size : 201.71kb
  • Downloaded :0次
  • Author :zhangxi
  • About : zhangxi
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
Wireless communication fpga design matlab, verilog code
Packet file list
(Preview for download)
Packet : 2581124805805.rar filelist
05805\matlab代码\matlab\c10\c.mat
05805\matlab代码\matlab\c10\costas.m
05805\matlab代码\matlab\c10\frame_syn.m
05805\matlab代码\matlab\c10\PLLC.m
05805\matlab代码\matlab\c10\RRCrece.m
05805\matlab代码\matlab\c10\RRCsend.m
05805\matlab代码\matlab\c10\symbol_syn.m
05805\matlab代码\matlab\c11\adpeq.m
05805\matlab代码\matlab\c11\ante.m
05805\matlab代码\matlab\c11\FFTlms.m
05805\matlab代码\matlab\c11\lms.m
05805\matlab代码\matlab\c11\RLS.m
05805\matlab代码\matlab\c11\signlms.m
05805\matlab代码\matlab\c11\WHT.m
05805\matlab代码\matlab\c11\WHTlms.m
05805\matlab代码\matlab\c12\correce.m
05805\matlab代码\matlab\c12\matchfil.m
05805\matlab代码\matlab\c12\rake.m
05805\matlab代码\matlab\c13\cell_search_cpich.m
05805\matlab代码\matlab\c13\ovsf.m
05805\matlab代码\matlab\c13\scramble.m
05805\matlab代码\matlab\c13\wcdmasource.m
05805\matlab代码\matlab\c6\impinvar_bilinear.m
05805\matlab代码\matlab\c6\rcosflt_filter.m
05805\matlab代码\matlab\c6\rcosine_filter.m
05805\matlab代码\matlab\c7\cicde.m
05805\matlab代码\matlab\c7\CICdec.m
05805\matlab代码\matlab\c7\cicin.m
05805\matlab代码\matlab\c7\CICinterp.m
05805\matlab代码\matlab\c7\halfdec.m
05805\matlab代码\matlab\c7\halfinterp.m
05805\matlab代码\matlab\c7\hbfil.m
05805\matlab代码\matlab\c7\multirece.m
05805\matlab代码\matlab\c7\multisend.m
05805\matlab代码\matlab\c8\ASKmod.m
05805\matlab代码\matlab\c8\F2T.m
05805\matlab代码\matlab\c8\LPF.m
05805\matlab代码\matlab\c8\MSKmod.m
05805\matlab代码\matlab\c8\OFDMmod.m
05805\matlab代码\matlab\c8\QAMmod.m
05805\matlab代码\matlab\c8\QPSKmod.m
05805\matlab代码\matlab\c8\T2F.m
05805\matlab代码\matlab\c9\convcode.m
05805\matlab代码\matlab\c9\CRCcheck.m
05805\matlab代码\matlab\c9\encoderm.m
05805\matlab代码\matlab\c9\encode_bit.m
05805\matlab代码\matlab\c9\hamming7_4.m
05805\matlab代码\matlab\c9\intrlvcode.m
05805\matlab代码\matlab\c9\RScode.m
05805\matlab代码\matlab\c9\rsc_encode.m
05805\matlab代码\matlab\c9\TCMcode.m
05805\Verilog代码\6、7.doc
05805\Verilog代码\c10\10-2\mult.xco
05805\Verilog代码\c10\10-2\mydds.xco
05805\Verilog代码\c10\10-2\square_syn.v
05805\Verilog代码\c10\10-4\coastas_dds.v
05805\Verilog代码\c10\10-4\costas_lf.v
05805\Verilog代码\c10\10-4\costas_loop.v
05805\Verilog代码\c10\10-4\costas_lpf.v
05805\Verilog代码\c10\10-4\costas_mult.v
05805\Verilog代码\c10\10-4\err_mult.v
05805\Verilog代码\c10\10-4\fir_lpf.xco
05805\Verilog代码\c10\10-4\mult.xco
05805\Verilog代码\c10\10-4\my_dds.xco
05805\Verilog代码\c10\10-6\dearly_sub.v
05805\Verilog代码\c10\10-6\dedds.v
05805\Verilog代码\c10\10-6\delay_early_gate.v
05805\Verilog代码\c10\10-6\de_mult.xco
05805\Verilog代码\c10\10-6\eddds.xco
05805\Verilog代码\c10\10-6\iir.v
05805\Verilog代码\c10\10-6\iir1.v
05805\Verilog代码\c10\10-8\baker.v
05805\Verilog代码\c11\11-10\div16.xco
05805\Verilog代码\c11\11-10\fir_rls.v
05805\Verilog代码\c11\11-10\rlsmult.xco
05805\Verilog代码\c11\11-10\shiftreg25.xco
05805\Verilog代码\c11\11-10\shiftreg28.xco
05805\Verilog代码\c11\11-10\shiftreg3.xco
05805\Verilog代码\c11\11-12\dfe_filter.v
05805\Verilog代码\c11\11-12\dfe_mult.xco
05805\Verilog代码\c11\11-14\aa_adder.xco
05805\Verilog代码\c11\11-14\aa_bram.xco
05805\Verilog代码\c11\11-14\aa_cmult.xco
05805\Verilog代码\c11\11-14\ad_a.v
05805\Verilog代码\c11\11-14\shift16.xco
05805\Verilog代码\c11\11-2\fir_lms.v
05805\Verilog代码\c11\11-3\fir_pipline_lms.v
05805\Verilog代码\c11\11-3\lmsmult.xco
05805\Verilog代码\c11\11-5\mult.xco
05805\Verilog代码\c11\11-5\shiftreg4.xco
05805\Verilog代码\c11\11-5\sign_fir_lms.v
05805\Verilog代码\c11\11-8\blockconnect.v
05805\Verilog代码\c11\11-8\cmult.v
05805\Verilog代码\c11\11-8\coe_updata.v
05805\Verilog代码\c11\11-8\complex_mult.xco
05805\Verilog代码\c11\11-8\fft_block.v
05805\Verilog代码\c11\11-8\fft_block_lms.v
05805\Verilog代码\c11\11-8\fft_w16_p32.xco
05805\Verilog代码\c11\11-8\gonge.v
05805\Verilog代码\c11\11-8\ifft_block.v
05805\Verilog代码\c11\11-8\insert.v
05805\Verilog代码\c11\11-8\save_sub.v
05805\Verilog代码\c11\11-8\shiftreg.xco
05805\Verilog代码\c11\11-8\shiftreg3.xco
05805\Verilog代码\c11\11-8\shift_reg2.xco
05805\Verilog代码\c11\11-8\srl16_w16_d16.xco
05805\Verilog代码\c11\11-8\test_block_connect.v
05805\Verilog代码\c12_0\12-6\rake_cmult.xco
05805\Verilog代码\c12_0\12-6\rake_mrc.v
05805\Verilog代码\c12_0\12-6\rake_shift4.xco
05805\Verilog代码\c13\13-2\ovsf.v
05805\Verilog代码\c13\13-3\Dscamb.v
05805\Verilog代码\c13\13-6\adder_18vs18.xco
05805\Verilog代码\c13\13-6\CPICH.v
05805\Verilog代码\c13\13-6\ram_1024.xco
05805\Verilog代码\c13\13-6\ram_descramb.xco
05805\Verilog代码\c3\3-22\adder8.v
05805\Verilog代码\c3\3-23\adder8_2.v
05805\Verilog代码\c3\3-24\adder8_4.v
05805\Verilog代码\c5\5-1\adder16_2.v
05805\Verilog代码\c5\5-10\div16.xco
05805\Verilog代码\c5\5-10\div16_1.v
05805\Verilog代码\c5\5-11\divf16.xco
05805\Verilog代码\c5\5-11\divf16_1.v
05805\Verilog代码\c5\5-15\dds.v
05805\Verilog代码\c5\5-15\rom_cos.coe
05805\Verilog代码\c5\5-15\rom_cose.xco
05805\Verilog代码\c5\5-15\rom_sin.coe
05805\Verilog代码\c5\5-15\rom_sine.xco
05805\Verilog代码\c5\5-16\dds1.v
05805\Verilog代码\c5\5-16\mydds.xco
05805\Verilog代码\c5\5-17\cordic.v
05805\Verilog代码\c5\5-18\sqrt.xco
05805\Verilog代码\c5\5-18\sqrt1.v
05805\Verilog代码\c5\5-2\add_4.v
05805\Verilog代码\c5\5-3\adder.xco
05805\Verilog代码\c5\5-3\adder1.v
05805\Verilog代码\c5\5-4\ade.v
05805\Verilog代码\c5\5-5\mul_addtree.v
05805\Verilog代码\c5\5-6\cmultip.v
05805\Verilog代码\c5\5-6\rmulti.xco
05805\Verilog代码\c5\5-7\mult_8.v
05805\Verilog代码\c5\5-9\divider.v
05805\Verilog代码\c6\6-15\IIR_Filter_8.v
05805\Verilog代码\c6\6-17\iir_c.v
05805\Verilog代码\c6\6-17\sub2.v
05805\Verilog代码\c6\6-18\iir_pipeline.v
05805\Verilog代码\c6\6-20\iir_par.v
05805\Verilog代码\c6\6-23\rrc_128.coe
05805\Verilog代码\c6\6-4\FIR_lowpass.v
05805\Verilog代码\c6\6-5\mult.xco
05805\Verilog代码\c6\6-5\ser_fir.v
05805\Verilog代码\c6\6-6\fir.v
05805\Verilog代码\c6\6-6\mult.xco
05805\Verilog代码\c6\6-7\da_fir.v
05805\Verilog代码\c6\6-7\DA_table.v
05805\Verilog代码\c7\7-10\cic_dec_8_three.v
05805\Verilog代码\c7\7-11\crc_interp_2_single.v
05805\Verilog代码\c7\7-12\cic_interp_8_three.v
05805\Verilog代码\c7\7-14\dsp48_core.xaw
05805\Verilog代码\c7\7-14\hb_filter.v
05805\Verilog代码\c7\7-14\lut16_core.xco
05805\Verilog代码\c7\7-16\cic2_interp.v
05805\Verilog代码\c7\7-16\cic4_interp4.v
05805\Verilog代码\c7\7-16\dds.xco
05805\Verilog代码\c7\7-16\fir16.v
05805\Verilog代码\c7\7-16\mydds.v
05805\Verilog代码\c7\7-16\rcf16.v
05805\Verilog代码\c7\7-16\rcf_dsp48.xco
05805\Verilog代码\c7\7-16\sender.v
05805\Verilog代码\c7\7-16\sender_fir.xco
05805\Verilog代码\c7\7-16\sender_modu.v
05805\Verilog代码\c7\7-16\send_mult.xco
05805\Verilog代码\c7\7-18\agc.v
05805\Verilog代码\c7\7-2\decimate_4.v
05805\Verilog代码\c7\7-20\filter_bank.v
05805\Verilog代码\c7\7-20\trellis_unit.v
05805\Verilog代码\c7\7-4\interpolate4.v
05805\Verilog代码\c7\7-5\rate4to3.v
05805\Verilog代码\c7\7-6\polyfilter.v
05805\Verilog代码\c7\7-9\crc_interp_2_single.v
05805\Verilog代码\c8\8-10\dds1_cosine.xco
05805\Verilog代码\c8\8-10\dds1_sine.xco
05805\Verilog代码\c8\8-10\dds_modu.xco
05805\Verilog代码\c8\8-10\iqmodu.v
05805\Verilog代码\c8\8-10\iqsin.v
05805\Verilog代码\c8\8-10\msk_mult.xco
05805\Verilog代码\c8\8-10\msk_top.v
05805\Verilog代码\c8\8-10\s2p.v
05805\Verilog代码\c8\8-12\ddsqam.xco
05805\Verilog代码\c8\8-12\qam16.v
05805\Verilog代码\c8\8-14\ofdm_fft.xco
05805\Verilog代码\c8\8-14\ofdm_modu.v
05805\Verilog代码\c8\8-2\two_ASK.v
05805\Verilog代码\c8\8-3\ASK_two.v
05805\Verilog代码\c8\8-5\QPSK.v
05805\Verilog代码\c8\8-6\QPSK_two.v
05805\Verilog代码\c8\8-8\two_fsk.v
05805\Verilog代码\c8\8-9\fsk_two.v
05805\Verilog代码\c8\8.doc
05805\Verilog代码\c9\9-10\conv_enc.v
05805\Verilog代码\c9\9-11\viterbi.v
05805\Verilog代码\c9\9-13\block_ram.xco
05805\Verilog代码\c9\9-13\interleaver.v
05805\Verilog代码\c9\9-16\tcm_enc.v
05805\Verilog代码\c9\9-2\linearcode.v
05805\Verilog代码\c9\9-2\lineardecode.v
05805\Verilog代码\c9\9-5\crc_16.v
05805\Verilog代码\c9\9-8\rs_enc.v
05805\Verilog代码\readme.txt
05805\缩略语表.doc
05805\matlab代码\matlab\c10
05805\matlab代码\matlab\c11
05805\matlab代码\matlab\c12
05805\matlab代码\matlab\c13
05805\matlab代码\matlab\c6
05805\matlab代码\matlab\c7
05805\matlab代码\matlab\c8
05805\matlab代码\matlab\c9
05805\Verilog代码\c10\10-2
05805\Verilog代码\c10\10-4
05805\Verilog代码\c10\10-6
05805\Verilog代码\c10\10-8
05805\Verilog代码\c11\11-10
05805\Verilog代码\c11\11-12
05805\Verilog代码\c11\11-14
05805\Verilog代码\c11\11-2
05805\Verilog代码\c11\11-3
05805\Verilog代码\c11\11-5
05805\Verilog代码\c11\11-8
05805\Verilog代码\c12_0\12-2_0
05805\Verilog代码\c12_0\12-4_0
05805\Verilog代码\c12_0\12-6
05805\Verilog代码\c13\13-2
05805\Verilog代码\c13\13-3
05805\Verilog代码\c13\13-6
05805\Verilog代码\c3\3-22
05805\Verilog代码\c3\3-23
05805\Verilog代码\c3\3-24
05805\Verilog代码\c5\5-1
05805\Verilog代码\c5\5-10
05805\Verilog代码\c5\5-11
05805\Verilog代码\c5\5-15
05805\Verilog代码\c5\5-16
05805\Verilog代码\c5\5-17
05805\Verilog代码\c5\5-18
05805\Verilog代码\c5\5-2
05805\Verilog代码\c5\5-3
05805\Verilog代码\c5\5-4
05805\Verilog代码\c5\5-5
05805\Verilog代码\c5\5-6
05805\Verilog代码\c5\5-7
05805\Verilog代码\c5\5-9
05805\Verilog代码\c6\6-15
05805\Verilog代码\c6\6-17
05805\Verilog代码\c6\6-18
05805\Verilog代码\c6\6-20
05805\Verilog代码\c6\6-23
05805\Verilog代码\c6\6-4
05805\Verilog代码\c6\6-5
05805\Verilog代码\c6\6-6
05805\Verilog代码\c6\6-7
05805\Verilog代码\c7\7-10
05805\Verilog代码\c7\7-11
05805\Verilog代码\c7\7-12
05805\Verilog代码\c7\7-14
05805\Verilog代码\c7\7-16
05805\Verilog代码\c7\7-17
05805\Verilog代码\c7\7-18
05805\Verilog代码\c7\7-2
05805\Verilog代码\c7\7-20
05805\Verilog代码\c7\7-4
05805\Verilog代码\c7\7-5
05805\Verilog代码\c7\7-6
05805\Verilog代码\c7\7-9
05805\Verilog代码\c8\8-10
05805\Verilog代码\c8\8-12
05805\Verilog代码\c8\8-14
05805\Verilog代码\c8\8-2
05805\Verilog代码\c8\8-3
05805\Verilog代码\c8\8-5
05805\Verilog代码\c8\8-6
05805\Verilog代码\c8\8-8
05805\Verilog代码\c8\8-9
05805\Verilog代码\c9\9-10
05805\Verilog代码\c9\9-11
05805\Verilog代码\c9\9-13
05805\Verilog代码\c9\9-16
05805\Verilog代码\c9\9-2
05805\Verilog代码\c9\9-5
05805\Verilog代码\c9\9-8
05805\matlab代码\matlab
05805\Verilog代码\c10
05805\Verilog代码\c11
05805\Verilog代码\c12_0
05805\Verilog代码\c13
05805\Verilog代码\c3
05805\Verilog代码\c5
05805\Verilog代码\c6
05805\Verilog代码\c7
05805\Verilog代码\c8
05805\Verilog代码\c9
05805\matlab代码
05805\Verilog代码
05805
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
DSSZ is the largest source code store in internet!
Contact us :
1999-2046 DSSZ All Rights Reserved.