Packet : 23825757an487_design_example.zip filelist
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/code/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/code/spi_to_i2s.v
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/spi_to_i2s.cr.mti
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/spi_to_i2s.mpf
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/spi_to_i2s.v
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/SPI_to_I2S_test.v
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/vsim.wlf
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/@s@p@i_to_@i2@s_test/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/i2s_master/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_slave/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/verilog.psm
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/_primary.dat
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/spi_to_i2s/_primary.vhd
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(0).cnf.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(0).cnf.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(1).cnf.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(1).cnf.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(2).cnf.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.(2).cnf.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.asm.qmsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.asm_labs.ddb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cbx.xml
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.logdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.rdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp.tdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.cmp0.ddb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.dbp
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.db_info
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.eco.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.fit.qmsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.hier_info
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.hif
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.logdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.map.qmsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.pre_map.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.pre_map.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.psp
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.pss
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.rtlv.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.rtlv_sg.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.rtlv_sg_swap.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sgdiff.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sgdiff.hdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.signalprobe.cdb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sld_design_entry.sci
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.sld_design_entry_dsc.sci
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.syn_hier_info
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.tan.qmsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/db/spi_to_i2s.tis_db_list.ddb
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.asm.rpt
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.done
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.fit.rpt
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.fit.smsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.fit.summary
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.flow.rpt
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.map.rpt
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.map.smsg
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.map.summary
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.pin
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.pof
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.qpf
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.qsf
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.qws
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.tan.rpt
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.tan.summary
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s.v
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/quartus/spi_to_i2s_assignment_defaults.qdf
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/testbench/
SPI_to_I2S_Altera_MAX_II_CPLD_Design_Example/testbench/SPI_to_I2S_test.v

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．