Packet : 93317458gpif_fifo_wr_rd.rar filelist
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.asm.rpt
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.cdf
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.done
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.fit.eqn
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.fit.rpt
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.fit.summary
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.flow.rpt
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.map.eqn
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.map.rpt
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.map.summary
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.pin
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.pof
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.qpf
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.qsf
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.qws
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.sim.rpt
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.sof
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.tan.rpt
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.tan.summary
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.vhd
GPIF_FIFO_WR_RD\FPGA\USB_FPGA.vwf
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.cmp.tdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.signalprobe.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.cmp.rdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.asm.qmsg
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.tan.qmsg
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.eco.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.cmp0.ddb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.cmp.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.cmp.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.sld_design_entry.sci
GPIF_FIFO_WR_RD\FPGA\db\altsyncram_lk81.tdf
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.db_info
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.sim.qmsg
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.map.qmsg
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.cmp.qrpt
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.cbx.xml
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.hif
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.(0).cnf.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.(0).cnf.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.hier_info
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.rtlv_sg.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.rtlv.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.rtlv_sg_swap.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.pre_map.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.pre_map.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.psp
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.dbp
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.(1).cnf.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.(1).cnf.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.(2).cnf.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.(2).cnf.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.sgdiff.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.sgdiff.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.sld_design_entry_dsc.sci
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.syn_hier_info
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.map.cdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.map.hdb
GPIF_FIFO_WR_RD\FPGA\db\USB_FPGA.fit.qmsg
GPIF_FIFO_WR_RD\FPGA\sopc_builder_debug_log.txt
GPIF_FIFO_WR_RD\FPGA\.sopc_builder\install.ptf
GPIF_FIFO_WR_RD\FPGA\talkback\USB_FPGA.map.talkback.xml
GPIF_FIFO_WR_RD\FPGA\talkback\USB_FPGA.fit.talkback.xml
GPIF_FIFO_WR_RD\FPGA\talkback\USB_FPGA.asm.talkback.xml
GPIF_FIFO_WR_RD\FPGA\talkback\USB_FPGA.tan.talkback.xml
GPIF_FIFO_WR_RD\GPIF\GPIF_FIFO_WR_RD.gpf
GPIF_FIFO_WR_RD\firmware\Ezusb.lib
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.LST
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.M51
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.OBJ
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.Uv2
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.bix
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.c
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.gpf
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.hex
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.iic
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.lnp
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.plg
GPIF_FIFO_WR_RD\firmware\GPIF_FIFO_WR_RD.gpf
GPIF_FIFO_WR_RD\firmware\Hex2Bix.bat
GPIF_FIFO_WR_RD\firmware\Hex2bix.exe
GPIF_FIFO_WR_RD\firmware\USBJmpTb.OBJ
GPIF_FIFO_WR_RD\firmware\dscr.LST
GPIF_FIFO_WR_RD\firmware\dscr.OBJ
GPIF_FIFO_WR_RD\firmware\dscr.a51
GPIF_FIFO_WR_RD\firmware\fw.LST
GPIF_FIFO_WR_RD\firmware\fw.OBJ
GPIF_FIFO_WR_RD\firmware\fw.c
GPIF_FIFO_WR_RD\firmware\gpif.LST
GPIF_FIFO_WR_RD\firmware\gpif.OBJ
GPIF_FIFO_WR_RD\firmware\gpif.c
GPIF_FIFO_WR_RD\firmware\readme.txt
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO_Opt.Bak
GPIF_FIFO_WR_RD\firmware\FX2_to_extsyncFIFO.Opt
GPIF_FIFO_WR_RD\FPGA\db
GPIF_FIFO_WR_RD\FPGA\.sopc_builder
GPIF_FIFO_WR_RD\FPGA\talkback
GPIF_FIFO_WR_RD\FPGA
GPIF_FIFO_WR_RD\GPIF
GPIF_FIFO_WR_RD\firmware
GPIF_FIFO_WR_RD

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