Packet : 7941963verilog_code.rar filelist
verilog_code\2sel1\_2sel1.qpf
verilog_code\2sel1\_2sel1.qsf
verilog_code\2sel1\db\wed.zsf
verilog_code\2sel1\db\_2sel1.db_info
verilog_code\2sel1\db\_2sel1.tan.qmsg
verilog_code\2sel1\db\_2sel1.fit.qmsg
verilog_code\2sel1\db\_2sel1.rtlv_sg_swap.cdb
verilog_code\2sel1\db\_2sel1.eda.qmsg
verilog_code\2sel1\db\_2sel1.cbx.xml
verilog_code\2sel1\db\_2sel1.cmp.logdb
verilog_code\2sel1\db\_2sel1.(0).cnf.cdb
verilog_code\2sel1\db\_2sel1.(0).cnf.hdb
verilog_code\2sel1\db\_2sel1.map.qmsg
verilog_code\2sel1\db\_2sel1.sim.qmsg
verilog_code\2sel1\db\_2sel1.sim.hdb
verilog_code\2sel1\db\_2sel1.hif
verilog_code\2sel1\db\_2sel1.eds_overflow
verilog_code\2sel1\db\_2sel1.sim.vwf
verilog_code\2sel1\db\_2sel1.hier_info
verilog_code\2sel1\db\_2sel1.sim.rdb
verilog_code\2sel1\db\_2sel1.map.logdb
verilog_code\2sel1\db\_2sel1.rtlv_sg.cdb
verilog_code\2sel1\db\_2sel1.rtlv.hdb
verilog_code\2sel1\db\_2sel1.pre_map.cdb
verilog_code\2sel1\db\_2sel1.pre_map.hdb
verilog_code\2sel1\db\_2sel1.psp
verilog_code\2sel1\db\_2sel1.dbp
verilog_code\2sel1\db\_2sel1.sgdiff.cdb
verilog_code\2sel1\db\_2sel1.sgdiff.hdb
verilog_code\2sel1\db\_2sel1.map.cdb
verilog_code\2sel1\db\_2sel1.map.hdb
verilog_code\2sel1\db\_2sel1.syn_hier_info
verilog_code\2sel1\db\_2sel1.asm.qmsg
verilog_code\2sel1\db\_2sel1.sld_design_entry_dsc.sci
verilog_code\2sel1\db\_2sel1.eco.cdb
verilog_code\2sel1\db\_2sel1.sld_design_entry.sci
verilog_code\2sel1\db\_2sel1.cmp.rdb
verilog_code\2sel1\db\_2sel1.cmp.tdb
verilog_code\2sel1\db\_2sel1.cmp.hdb
verilog_code\2sel1\db\_2sel1.cmp0.ddb
verilog_code\2sel1\db\_2sel1.cmp.cdb
verilog_code\2sel1\_2sel1.v
verilog_code\2sel1\_2sel1.map.rpt
verilog_code\2sel1\_2sel1.flow.rpt
verilog_code\2sel1\_2sel1.map.summary
verilog_code\2sel1\_2sel1.dpf
verilog_code\2sel1\_2sel1.pin
verilog_code\2sel1\_2sel1.fit.rpt
verilog_code\2sel1\_2sel1.fit.summary
verilog_code\2sel1\_2sel1.sof
verilog_code\2sel1\_2sel1.pof
verilog_code\2sel1\_2sel1.asm.rpt
verilog_code\2sel1\_2sel1.tan.summary
verilog_code\2sel1\_2sel1.tan.rpt
verilog_code\2sel1\simulation\activehdl\_2sel1.vo
verilog_code\2sel1\simulation\activehdl\_2sel1_v.sdo
verilog_code\2sel1\timing\primetime\_2sel1.vho
verilog_code\2sel1\timing\primetime\_2sel1_vhd.sdo
verilog_code\2sel1\timing\primetime\_2sel1_pt_vhd.tcl
verilog_code\2sel1\_2sel1.eda.rpt
verilog_code\2sel1\_2sel1.done
verilog_code\2sel1\_2sel1.vwf
verilog_code\2sel1\_2sel1.sim.rpt
verilog_code\2sel1\_2sel1.cdf
verilog_code\2sel1\sopc_builder_debug_log.txt
verilog_code\2sel1\.sopc_builder\install.ptf
verilog_code\2sel1\资料\编辑代码.bmp
verilog_code\2sel1\资料\编辑引脚.bmp
verilog_code\2sel1\资料\综合成功.bmp
verilog_code\2sel1\资料\仿真成功.bmp
verilog_code\2sel1\资料\下载成功.bmp
verilog_code\2sel1\资料\Thumbs.db
verilog_code\2sel1\资料\操作说明.txt
verilog_code\2sel1\_2sel1.qws
verilog_code\_8bitFullAdd\_8bitFullAdd.qpf
verilog_code\_8bitFullAdd\_8bitFullAdd.qsf
verilog_code\_8bitFullAdd\db\wed.zsf
verilog_code\_8bitFullAdd\db\_8bitFullAdd.db_info
verilog_code\_8bitFullAdd\db\_8bitFullAdd.cmp0.ddb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.cmp.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.eco.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sim.qmsg
verilog_code\_8bitFullAdd\db\_8bitFullAdd.map.qmsg
verilog_code\_8bitFullAdd\db\_8bitFullAdd.cmp.rdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.cbx.xml
verilog_code\_8bitFullAdd\db\_8bitFullAdd.hif
verilog_code\_8bitFullAdd\db\_8bitFullAdd.cmp.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(0).cnf.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.eda.qmsg
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(0).cnf.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.hier_info
verilog_code\_8bitFullAdd\db\_8bitFullAdd.rtlv_sg.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.rtlv.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.rtlv_sg_swap.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sim.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.pre_map.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sim.vwf
verilog_code\_8bitFullAdd\db\_8bitFullAdd.pre_map.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.psp
verilog_code\_8bitFullAdd\db\_8bitFullAdd.dbp
verilog_code\_8bitFullAdd\db\add_sub_djh.tdf
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sim.rdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(1).cnf.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sld_design_entry.sci
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(1).cnf.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(2).cnf.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(2).cnf.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(3).cnf.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(3).cnf.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(4).cnf.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(4).cnf.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(5).cnf.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(5).cnf.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(6).cnf.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.(6).cnf.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.map.logdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sgdiff.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sgdiff.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.sld_design_entry_dsc.sci
verilog_code\_8bitFullAdd\db\_8bitFullAdd.syn_hier_info
verilog_code\_8bitFullAdd\db\_8bitFullAdd.map.cdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.map.hdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.fit.qmsg
verilog_code\_8bitFullAdd\db\_8bitFullAdd.cmp.logdb
verilog_code\_8bitFullAdd\db\_8bitFullAdd.asm.qmsg
verilog_code\_8bitFullAdd\db\_8bitFullAdd.tan.qmsg
verilog_code\_8bitFullAdd\db\_8bitFullAdd.cmp.tdb
verilog_code\_8bitFullAdd\_8bitFullAdd.v
verilog_code\_8bitFullAdd\_8bitFullAdd.qws
verilog_code\_8bitFullAdd\_8bitFullAdd.vwf
verilog_code\_8bitFullAdd\_8bitFullAdd.map.rpt
verilog_code\_8bitFullAdd\_8bitFullAdd.flow.rpt
verilog_code\_8bitFullAdd\_8bitFullAdd.map.summary
verilog_code\_8bitFullAdd\_8bitFullAdd.pin
verilog_code\_8bitFullAdd\_8bitFullAdd.fit.rpt
verilog_code\_8bitFullAdd\_8bitFullAdd.fit.summary
verilog_code\_8bitFullAdd\_8bitFullAdd.sof
verilog_code\_8bitFullAdd\_8bitFullAdd.pof
verilog_code\_8bitFullAdd\_8bitFullAdd.asm.rpt
verilog_code\_8bitFullAdd\_8bitFullAdd.tan.summary
verilog_code\_8bitFullAdd\_8bitFullAdd.tan.rpt
verilog_code\_8bitFullAdd\simulation\activehdl\_8bitFullAdd.vo
verilog_code\_8bitFullAdd\simulation\activehdl\_8bitFullAdd_v.sdo
verilog_code\_8bitFullAdd\timing\primetime\_8bitFullAdd.vho
verilog_code\_8bitFullAdd\timing\primetime\_8bitFullAdd_vhd.sdo
verilog_code\_8bitFullAdd\timing\primetime\_8bitFullAdd_pt_vhd.tcl
verilog_code\_8bitFullAdd\_8bitFullAdd.eda.rpt
verilog_code\_8bitFullAdd\_8bitFullAdd.done
verilog_code\_8bitFullAdd\_8bitFullAdd.sim.rpt
verilog_code\_8bitFullAdd\资料\仿真.bmp
verilog_code\_8bitFullAdd\资料\代码.bmp
verilog_code\testlist\testlist.qpf
verilog_code\testlist\testlist.qsf
verilog_code\testlist\db\wed.zsf
verilog_code\testlist\db\testlist.db_info
verilog_code\testlist\db\testlist.asm.qmsg
verilog_code\testlist\db\testlist.cmp.rdb
verilog_code\testlist\db\testlist.cmp.tdb
verilog_code\testlist\db\testlist.cmp.hdb
verilog_code\testlist\db\testlist.cbx.xml
verilog_code\testlist\db\testlist.tan.qmsg
verilog_code\testlist\db\testlist.eda.qmsg
verilog_code\testlist\db\testlist.cmp0.ddb
verilog_code\testlist\db\testlist.cmp.cdb
verilog_code\testlist\db\testlist.sim.qmsg
verilog_code\testlist\db\testlist.hif
verilog_code\testlist\db\testlist.sim.hdb
verilog_code\testlist\db\testlist.sim.vwf
verilog_code\testlist\db\testlist.hier_info
verilog_code\testlist\db\testlist.sim.rdb
verilog_code\testlist\db\testlist.sld_design_entry.sci
verilog_code\testlist\db\testlist.eco.cdb
verilog_code\testlist\db\testlist.psp
verilog_code\testlist\db\testlist.dbp
verilog_code\testlist\db\testlist.syn_hier_info
verilog_code\testlist\db\testlist.(0).cnf.cdb
verilog_code\testlist\db\testlist.(0).cnf.hdb
verilog_code\testlist\db\testlist.map.qmsg
verilog_code\testlist\db\testlist.rtlv_sg.cdb
verilog_code\testlist\db\testlist.rtlv.hdb
verilog_code\testlist\db\testlist.rtlv_sg_swap.cdb
verilog_code\testlist\db\testlist.pre_map.hdb
verilog_code\testlist\db\testlist.pre_map.cdb
verilog_code\testlist\db\testlist.map.logdb
verilog_code\testlist\db\testlist.sgdiff.cdb
verilog_code\testlist\db\testlist.sgdiff.hdb
verilog_code\testlist\db\testlist.sld_design_entry_dsc.sci
verilog_code\testlist\db\testlist.map.cdb
verilog_code\testlist\db\testlist.map.hdb
verilog_code\testlist\db\testlist.fit.qmsg
verilog_code\testlist\db\testlist.cmp.logdb
verilog_code\testlist\testlist.v
verilog_code\testlist\testlist.map.rpt
verilog_code\testlist\testlist.flow.rpt
verilog_code\testlist\testlist.map.summary
verilog_code\testlist\testlist.done
verilog_code\testlist\testlist.pin
verilog_code\testlist\testlist.fit.rpt
verilog_code\testlist\testlist.fit.summary
verilog_code\testlist\testlist.sof
verilog_code\testlist\testlist.pof
verilog_code\testlist\testlist.asm.rpt
verilog_code\testlist\testlist.dpf
verilog_code\testlist\testlist.tan.summary
verilog_code\testlist\testlist.tan.rpt
verilog_code\testlist\simulation\activehdl\testlist.vo
verilog_code\testlist\simulation\activehdl\testlist_v.sdo
verilog_code\testlist\timing\primetime\testlist.vho
verilog_code\testlist\timing\primetime\testlist_vhd.sdo
verilog_code\testlist\timing\primetime\testlist_pt_vhd.tcl
verilog_code\testlist\testlist.eda.rpt
verilog_code\testlist\testlist.vwf
verilog_code\testlist\testlist.cdf
verilog_code\testlist\testlist.sim.rpt
verilog_code\testlist\资料\仿真成功.bmp
verilog_code\testlist\资料\下载成功.bmp
verilog_code\testlist\资料\配置引脚.bmp
verilog_code\testlist\资料\综合成功.bmp
verilog_code\testlist\资料\代码.bmp
verilog_code\testlist\testlist.qws
verilog_code\2sel1\simulation\activehdl
verilog_code\2sel1\timing\primetime
verilog_code\_8bitFullAdd\simulation\activehdl
verilog_code\_8bitFullAdd\timing\primetime
verilog_code\testlist\simulation\activehdl
verilog_code\testlist\timing\primetime
verilog_code\2sel1\db
verilog_code\2sel1\simulation
verilog_code\2sel1\timing
verilog_code\2sel1\.sopc_builder
verilog_code\2sel1\资料
verilog_code\_8bitFullAdd\db
verilog_code\_8bitFullAdd\simulation
verilog_code\_8bitFullAdd\timing
verilog_code\_8bitFullAdd\资料
verilog_code\testlist\db
verilog_code\testlist\simulation
verilog_code\testlist\timing
verilog_code\testlist\资料
verilog_code\2sel1
verilog_code\_8bitFullAdd
verilog_code\testlist
verilog_code

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