This is a design using Verilog language and the digital frequency of the source code, upload click for U.S. research

Packet : 79419137verilog.rar filelist
main\main.qpf
main\main.qsf
main\main.bdf
main\dispselect.v
main\data_mux.v
main\dispdecoder.v
main\fdiv.v
main\flip_latch.v
main\main.map.eqn
main\main.map.rpt
main\main.flow.rpt
main\main.map.summary
main\main.fit.eqn
main\main.pin
main\main.fit.rpt
main\main.fit.summary
main\main.pof
main\main.asm.rpt
main\main.tan.summary
main\main.tan.rpt
main\main.done
main\main.sim.rpt
main\main.vwf
main\counter.v
main\gate_control.v
main\main.v
main\main.qws
main\cmp_state.ini
main\db\main.db_info
main\db\main.eco.cdb
main\db\main.map.qmsg
main\db\main.(1).cnf.cdb
main\db\main.cmp.rdb
main\db\main.(1).cnf.hdb
main\db\main.pre_map.hdb
main\db\main.pre_map.cdb
main\db\main.rtlv.hdb
main\db\main.hif
main\db\main.(0).cnf.cdb
main\db\main.(0).cnf.hdb
main\db\main.(2).cnf.cdb
main\db\main.rtlv_sg_swap.cdb
main\db\main.(2).cnf.hdb
main\db\main.rtlv_sg.cdb
main\db\main.(3).cnf.cdb
main\db\main.(3).cnf.hdb
main\db\main.(4).cnf.cdb
main\db\main.(4).cnf.hdb
main\db\main.(5).cnf.cdb
main\db\main.(5).cnf.hdb
main\db\main.(6).cnf.cdb
main\db\main.(6).cnf.hdb
main\db\main.(7).cnf.cdb
main\db\main.(7).cnf.hdb
main\db\main.hier_info
main\db\main.fit.qmsg
main\db\main.asm.qmsg
main\db\main.sgdiff.cdb
main\db\main.map.hdb
main\db\main.sgdiff.hdb
main\db\main.psp
main\db\main.(8).cnf.cdb
main\db\main.(8).cnf.hdb
main\db\main.(9).cnf.cdb
main\db\main.(9).cnf.hdb
main\db\main.cmp.hdb
main\db\main.tan.qmsg
main\db\main.(10).cnf.cdb
main\db\main.(10).cnf.hdb
main\db\main.sim.qmsg
main\db\main.sim.vwf
main\db\main.map.cdb
main\db\main.cmp.cdb
main\db\main.cmp.ddb
main\db\main.sld_design_entry.sci
main\db\main.syn_hier_info
main\db\main.sim.rdb
main\db\main.sim.hdb
main\db\main.cmp.tdb
main\db\main.cmp0.ddb
main\db\main.sld_design_entry_dsc.sci
main\db\main_cmp.qrpt
main\db\main_sim.qrpt
main\db\main.eds_overflow
main\db
main

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