This is a design using the VHDL language elevator control procedures, along with simulation timing diagram.

Packet : 75448159elvator_control_base_on_fpga.rar filelist
dianti\dianti(1).cnf
dianti\dianti(2).cnf
dianti\dianti(3).cnf
dianti\dianti(4).cnf
dianti\dianti(5).cnf
dianti\dianti.acf
dianti\dianti.cnf
dianti\dianti.fit
dianti\dianti.hex
dianti\dianti.hif
dianti\dianti.mmf
dianti\dianti.ndb
dianti\dianti.pin
dianti\dianti.pof
dianti\dianti.rpt
dianti\dianti.scf
dianti\dianti.snf
dianti\dianti.sof
dianti\DIANTI.sym
dianti\dianti.ttf
dianti\dianti.vhd
dianti\LIB.DLS
dianti\system(1).cnf
dianti\system(2).cnf
dianti\system(3).cnf
dianti\system(4).cnf
dianti\system(5).cnf
dianti\system.acf
dianti\system.cnf
dianti\system.fit
dianti\system.gdf
dianti\system.hex
dianti\system.hif
dianti\system.mmf
dianti\system.ndb
dianti\system.pin
dianti\system.pof
dianti\system.rpt
dianti\system.scf
dianti\system.snf
dianti\system.sof
dianti\system.ttf
dianti\U1121839.DLS
dianti\U4473885.DLS
dianti\U8390567.DLS
图\1.JPG
图\2.JPG
图\3.JPG
图\Backup of Copy of wei
图\Backup of wei
图\MyDesign1.ddb
图\Previous Backup of Copy of wei
图\wei.Bkp
图\wei.Ddb
dianti
图

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