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  • Update : 2018-02-12
  • Size : 157kb
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  • Author :王一9
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FPGA implementation decoder
Packet file list
(Preview for download)
FilenameSizeUpdate
06_bcd\prj\BCD_Counter.pti_db_list.ddb 296 2018-01-26
06_bcd\prj\BCD_Counter.qpf 1282 2018-01-25
06_bcd\prj\BCD_Counter.qsf 4060 2018-01-26
06_bcd\prj\BCD_Counter.qws 3168 2018-01-26
06_bcd\prj\BCD_Counter.rar 703 2018-02-12
06_bcd\prj\BCD_Counter.tis_db_list.ddb 296 2018-01-26
06_bcd\prj\BCD_Counter_nativelink_simulation.rpt 994 2018-01-26
06_bcd\prj\db\BCD_Counter.(0).cnf.cdb 1690 2018-01-26
06_bcd\prj\db\BCD_Counter.(0).cnf.hdb 839 2018-01-26
06_bcd\prj\db\BCD_Counter.(1).cnf.cdb 1661 2018-01-26
06_bcd\prj\db\BCD_Counter.(1).cnf.hdb 1002 2018-01-26
06_bcd\prj\db\BCD_Counter.cbx.xml 93 2018-01-26
06_bcd\prj\db\BCD_Counter.cmp.rdb 5706 2018-01-26
06_bcd\prj\db\BCD_Counter.cmp_merge.kpt 215 2018-01-26
06_bcd\prj\db\BCD_Counter.db_info 140 2018-01-26
06_bcd\prj\db\BCD_Counter.eco.cdb 164 2018-01-26
06_bcd\prj\db\BCD_Counter.hier_info 2050 2018-01-26
06_bcd\prj\db\BCD_Counter.hif 519 2018-01-26
06_bcd\prj\db\BCD_Counter.ipinfo 163 2018-01-26
06_bcd\prj\db\BCD_Counter.lpc.html 993 2018-01-26
06_bcd\prj\db\BCD_Counter.lpc.rdb 470 2018-01-26
06_bcd\prj\db\BCD_Counter.lpc.txt 1935 2018-01-26
06_bcd\prj\db\BCD_Counter.map.ammdb 129 2018-01-26
06_bcd\prj\db\BCD_Counter.map.bpm 730 2018-01-26
06_bcd\prj\db\BCD_Counter.map.cdb 4194 2018-01-26
06_bcd\prj\db\BCD_Counter.map.hdb 11288 2018-01-26
06_bcd\prj\db\BCD_Counter.map.kpt 570 2018-01-26
06_bcd\prj\db\BCD_Counter.map.logdb 4 2018-01-26
06_bcd\prj\db\BCD_Counter.map.qmsg 7442 2018-01-26
06_bcd\prj\db\BCD_Counter.map.rdb 1311 2018-01-26
06_bcd\prj\db\BCD_Counter.map_bb.cdb 1938 2018-01-26
06_bcd\prj\db\BCD_Counter.map_bb.hdb 9839 2018-01-26
06_bcd\prj\db\BCD_Counter.map_bb.logdb 4 2018-01-26
06_bcd\prj\db\BCD_Counter.npp.qmsg 2127 2018-01-26
06_bcd\prj\db\BCD_Counter.pre_map.hdb 11235 2018-01-26
06_bcd\prj\db\BCD_Counter.pti_db_list.ddb 246 2018-01-26
06_bcd\prj\db\BCD_Counter.root_partition.map.reg_db.cdb 225 2018-01-26
06_bcd\prj\db\BCD_Counter.rtlv.hdb 11136 2018-01-26
06_bcd\prj\db\BCD_Counter.rtlv_sg.cdb 2682 2018-01-26
06_bcd\prj\db\BCD_Counter.rtlv_sg_swap.cdb 699 2018-01-26
06_bcd\prj\db\BCD_Counter.sgate.nvd 3858 2018-01-26
06_bcd\prj\db\BCD_Counter.sgate_sm.nvd 244 2018-01-26
06_bcd\prj\db\BCD_Counter.sgdiff.cdb 3912 2018-01-26
06_bcd\prj\db\BCD_Counter.sgdiff.hdb 11137 2018-01-26
06_bcd\prj\db\BCD_Counter.sld_design_entry.sci 277 2018-01-26
06_bcd\prj\db\BCD_Counter.sld_design_entry_dsc.sci 277 2018-01-26
06_bcd\prj\db\BCD_Counter.smart_action.txt 5 2018-01-26
06_bcd\prj\db\BCD_Counter.tis_db_list.ddb 246 2018-01-26
06_bcd\prj\db\logic_util_heursitic.dat 0 2018-01-26
06_bcd\prj\db\prev_cmp_BCD_Counter.qmsg 10370 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.db_info 140 2018-01-25
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.cdb 3954 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.dpi 799 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.hbdb.cdb 1445 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.hbdb.hb_info 46 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.hbdb.hdb 11005 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.hbdb.sig 32 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.hdb 11153 2018-01-26
06_bcd\prj\incremental_db\compiled_partitions\BCD_Counter.root_partition.map.kpt 576 2018-01-26
06_bcd\prj\incremental_db\README 653 2018-01-25
06_bcd\prj\output_files\BCD_Counter.done 26 2018-01-26
06_bcd\prj\output_files\BCD_Counter.flow.rpt 8705 2018-01-26
06_bcd\prj\output_files\BCD_Counter.map.rpt 22667 2018-01-26
06_bcd\prj\output_files\BCD_Counter.map.summary 480 2018-01-26
06_bcd\prj\simulation\modelsim\BCD_Counter_run_msim_rtl_verilog.do 781 2018-01-26
06_bcd\prj\simulation\modelsim\BCD_Counter_run_msim_rtl_verilog.do.bak 632 2018-01-25
06_bcd\prj\simulation\modelsim\BCD_Counter_run_msim_rtl_verilog.do.bak1 781 2018-01-26
06_bcd\prj\simulation\modelsim\modelsim.ini 11131 2018-01-26
06_bcd\prj\simulation\modelsim\msim_transcript 3641 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter\verilog.prw 323 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter\verilog.psm 5696 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter\_primary.dat 584 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter\_primary.dbs 794 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter\_primary.vhd 332 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top\verilog.prw 182 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top\verilog.psm 6176 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top\_primary.dat 719 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top\_primary.dbs 1116 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top\_primary.vhd 341 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top_tb\verilog.prw 601 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top_tb\verilog.psm 6456 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top_tb\_primary.dat 701 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top_tb\_primary.dbs 1271 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top_tb\_primary.vhd 96 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\_info 2071 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\_vmake 26 2018-01-26
06_bcd\prj\simulation\modelsim\vsim.wlf 843776 2018-01-26
06_bcd\rtl\BCD_Counter.v 599 2018-01-26
06_bcd\rtl\BCD_Counter.v.bak 616 2018-01-25
06_bcd\rtl\BCD_Counter_top.v 757 2018-01-26
06_bcd\rtl\BCD_Counter_top.v.bak 555 2018-01-25
06_bcd\testbench\BCD_Counter_tb.v 553 2018-01-26
06_bcd\testbench\BCD_Counter_tb.v.bak 545 2018-01-25
06_bcd\testbench\BCD_Counter_top_tb.v 517 2018-01-26
06_bcd\testbench\BCD_Counter_top_tb.v.bak 513 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter 0 2018-02-10
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top 0 2018-02-10
06_bcd\prj\simulation\modelsim\rtl_work\@b@c@d_@counter_top_tb 0 2018-02-10
06_bcd\prj\simulation\modelsim\rtl_work\_temp 0 2018-01-26
06_bcd\prj\simulation\modelsim\rtl_work 0 2018-02-10
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