Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.

Packet : 91332005clock.rar filelist
clock\Block1.bdf
clock\db\REL_clock.(0).cnf.cdb
clock\db\REL_clock.(0).cnf.hdb
clock\db\REL_clock.analyze_file.qmsg
clock\db\REL_clock.asm.qmsg
clock\db\REL_clock.cbx.xml
clock\db\REL_clock.cmp.cdb
clock\db\REL_clock.cmp.hdb
clock\db\REL_clock.cmp.kpt
clock\db\REL_clock.cmp.logdb
clock\db\REL_clock.cmp.rdb
clock\db\REL_clock.cmp.tdb
clock\db\REL_clock.cmp0.ddb
clock\db\REL_clock.dbp
clock\db\REL_clock.db_info
clock\db\REL_clock.eco.cdb
clock\db\REL_clock.eds_overflow
clock\db\REL_clock.fit.qmsg
clock\db\REL_clock.hier_info
clock\db\REL_clock.hif
clock\db\REL_clock.map.cdb
clock\db\REL_clock.map.hdb
clock\db\REL_clock.map.logdb
clock\db\REL_clock.map.qmsg
clock\db\REL_clock.pre_map.cdb
clock\db\REL_clock.pre_map.hdb
clock\db\REL_clock.psp
clock\db\REL_clock.rtlv.hdb
clock\db\REL_clock.rtlv_sg.cdb
clock\db\REL_clock.rtlv_sg_swap.cdb
clock\db\REL_clock.sgdiff.cdb
clock\db\REL_clock.sgdiff.hdb
clock\db\REL_clock.signalprobe.cdb
clock\db\REL_clock.sim.hdb
clock\db\REL_clock.sim.qmsg
clock\db\REL_clock.sim.rdb
clock\db\REL_clock.sim.vwf
clock\db\REL_clock.sld_design_entry.sci
clock\db\REL_clock.sld_design_entry_dsc.sci
clock\db\REL_clock.syn_hier_info
clock\db\REL_clock.tan.qmsg
clock\db\wed.zsf
clock\REL_clock.asm.rpt
clock\REL_clock.done
clock\REL_clock.fit.rpt
clock\REL_clock.fit.smsg
clock\REL_clock.fit.summary
clock\REL_clock.flow.rpt
clock\REL_clock.map.rpt
clock\REL_clock.map.summary
clock\REL_clock.pin
clock\REL_clock.pof
clock\REL_clock.qpf
clock\REL_clock.qsf
clock\REL_clock.qws
clock\REL_clock.sim.rpt
clock\REL_clock.sof
clock\REL_clock.tan.rpt
clock\REL_clock.tan.summary
clock\REL_clock.vhd
clock\REL_clock.vwf
clock\REL_clock_description.txt
clock\shuzizhong.bsf
clock\db
clock

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