Introduction - If you have any usage issues, please Google them yourself
This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.
Packet : 49636946verilog_example.rar filelist
Verilog源码例子\6分频\G5f.v
Verilog源码例子\6分频\tb_g5f.v
Verilog源码例子\6分频
Verilog源码例子\adder\ise\adder\.untf
Verilog源码例子\adder\ise\adder\adder.bgn
Verilog源码例子\adder\ise\adder\adder.bit
Verilog源码例子\adder\ise\adder\adder.bld
Verilog源码例子\adder\ise\adder\adder.cmd_log
Verilog源码例子\adder\ise\adder\adder.dhp
Verilog源码例子\adder\ise\adder\adder.drc
Verilog源码例子\adder\ise\adder\adder.lfp
Verilog源码例子\adder\ise\adder\adder.lso
Verilog源码例子\adder\ise\adder\adder.mrp
Verilog源码例子\adder\ise\adder\adder.nc1
Verilog源码例子\adder\ise\adder\adder.ncd
Verilog源码例子\adder\ise\adder\adder.ngc
Verilog源码例子\adder\ise\adder\adder.ngd
Verilog源码例子\adder\ise\adder\adder.ngm
Verilog源码例子\adder\ise\adder\adder.ngr
Verilog源码例子\adder\ise\adder\adder.npl
Verilog源码例子\adder\ise\adder\adder.pad
Verilog源码例子\adder\ise\adder\adder.pad_txt
Verilog源码例子\adder\ise\adder\adder.par
Verilog源码例子\adder\ise\adder\adder.pcf
Verilog源码例子\adder\ise\adder\adder.placed_ncd_tracker
Verilog源码例子\adder\ise\adder\adder.prj
Verilog源码例子\adder\ise\adder\adder.routed_ncd_tracker
Verilog源码例子\adder\ise\adder\adder.stx
Verilog源码例子\adder\ise\adder\adder.syr
Verilog源码例子\adder\ise\adder\adder.twr
Verilog源码例子\adder\ise\adder\adder.twx
Verilog源码例子\adder\ise\adder\adder.ucf
Verilog源码例子\adder\ise\adder\adder.ucf.untf
Verilog源码例子\adder\ise\adder\adder.ut
Verilog源码例子\adder\ise\adder\adder.v
Verilog源码例子\adder\ise\adder\adder.xpi
Verilog源码例子\adder\ise\adder\adder_map.ncd
Verilog源码例子\adder\ise\adder\adder_map.ngm
Verilog源码例子\adder\ise\adder\adder_pad.csv
Verilog源码例子\adder\ise\adder\adder_pad.txt
Verilog源码例子\adder\ise\adder\adder_vhdl.prj
Verilog源码例子\adder\ise\adder\automake.log
Verilog源码例子\adder\ise\adder\bitgen.ut
Verilog源码例子\adder\ise\adder\xst\work\hdllib.ref
Verilog源码例子\adder\ise\adder\xst\work\vlg54\adder.bin
Verilog源码例子\adder\ise\adder\xst\work\vlg54
Verilog源码例子\adder\ise\adder\xst\work
Verilog源码例子\adder\ise\adder\xst
Verilog源码例子\adder\ise\adder\_ngo\netlist.lst
Verilog源码例子\adder\ise\adder\_ngo
Verilog源码例子\adder\ise\adder\__projnav\adder.gfl
Verilog源码例子\adder\ise\adder\__projnav\adder.xst
Verilog源码例子\adder\ise\adder\__projnav\adder_flowplus.gfl
Verilog源码例子\adder\ise\adder\__projnav\adder_ncdTOut_tcl.rsp
Verilog源码例子\adder\ise\adder\__projnav\bitgen.rsp
Verilog源码例子\adder\ise\adder\__projnav\ednTOngd_tcl.rsp
Verilog源码例子\adder\ise\adder\__projnav\map.log
Verilog源码例子\adder\ise\adder\__projnav\nc1TOncd_tcl.rsp
Verilog源码例子\adder\ise\adder\__projnav\par.log
Verilog源码例子\adder\ise\adder\__projnav\parentAssignPackagePinsApp_tcl.rsp
Verilog源码例子\adder\ise\adder\__projnav\posttrc.log
Verilog源码例子\adder\ise\adder\__projnav\runXst_tcl.rsp
Verilog源码例子\adder\ise\adder\__projnav
Verilog源码例子\adder\ise\adder\__projnav.log
Verilog源码例子\adder\ise\adder
Verilog源码例子\adder\ise
Verilog源码例子\adder\modelsim\adder.cr.mti
Verilog源码例子\adder\modelsim\adder.mpf
Verilog源码例子\adder\modelsim\vsim.wlf
Verilog源码例子\adder\modelsim\work\adder\verilog.asm
Verilog源码例子\adder\modelsim\work\adder\_primary.dat
Verilog源码例子\adder\modelsim\work\adder\_primary.vhd
Verilog源码例子\adder\modelsim\work\adder
Verilog源码例子\adder\modelsim\work\tb_adder\verilog.asm
Verilog源码例子\adder\modelsim\work\tb_adder\_primary.dat
Verilog源码例子\adder\modelsim\work\tb_adder\_primary.vhd
Verilog源码例子\adder\modelsim\work\tb_adder
Verilog源码例子\adder\modelsim\work\_info
Verilog源码例子\adder\modelsim\work
Verilog源码例子\adder\modelsim
Verilog源码例子\adder\rtl\adder.v
Verilog源码例子\adder\rtl\tb_adder.v
Verilog源码例子\adder\rtl
Verilog源码例子\adder
Verilog源码例子\comparator\ISE\comparator\.untf
Verilog源码例子\comparator\ISE\comparator\automake.log
Verilog源码例子\comparator\ISE\comparator\bitgen.ut
Verilog源码例子\comparator\ISE\comparator\comparator.bgn
Verilog源码例子\comparator\ISE\comparator\comparator.bit
Verilog源码例子\comparator\ISE\comparator\comparator.bld
Verilog源码例子\comparator\ISE\comparator\comparator.cmd_log
Verilog源码例子\comparator\ISE\comparator\comparator.dhp
Verilog源码例子\comparator\ISE\comparator\comparator.drc
Verilog源码例子\comparator\ISE\comparator\comparator.lso
Verilog源码例子\comparator\ISE\comparator\comparator.mrp
Verilog源码例子\comparator\ISE\comparator\comparator.nc1
Verilog源码例子\comparator\ISE\comparator\comparator.ncd
Verilog源码例子\comparator\ISE\comparator\comparator.ngc
Verilog源码例子\comparator\ISE\comparator\comparator.ngd
Verilog源码例子\comparator\ISE\comparator\comparator.ngm
Verilog源码例子\comparator\ISE\comparator\comparator.ngr
Verilog源码例子\comparator\ISE\comparator\comparator.npl
Verilog源码例子\comparator\ISE\comparator\comparator.pad
Verilog源码例子\comparator\ISE\comparator\comparator.pad_txt
Verilog源码例子\comparator\ISE\comparator\comparator.par
Verilog源码例子\comparator\ISE\comparator\comparator.pcf
Verilog源码例子\comparator\ISE\comparator\comparator.placed_ncd_tracker
Verilog源码例子\comparator\ISE\comparator\comparator.prj
Verilog源码例子\comparator\ISE\comparator\comparator.routed_ncd_tracker
Verilog源码例子\comparator\ISE\comparator\comparator.stx
Verilog源码例子\comparator\ISE\comparator\comparator.syr
Verilog源码例子\comparator\ISE\comparator\comparator.twr
Verilog源码例子\comparator\ISE\comparator\comparator.twx
Verilog源码例子\comparator\ISE\comparator\comparator.ucf
Verilog源码例子\comparator\ISE\comparator\comparator.ucf.bak
Verilog源码例子\comparator\ISE\comparator\comparator.ucf.untf
Verilog源码例子\comparator\ISE\comparator\comparator.ut
Verilog源码例子\comparator\ISE\comparator\comparator.v
Verilog源码例子\comparator\ISE\comparator\comparator.xpi
Verilog源码例子\comparator\ISE\comparator\comparator_map.ncd
Verilog源码例子\comparator\ISE\comparator\comparator_map.ngm
Verilog源码例子\comparator\ISE\comparator\comparator_pad.csv
Verilog源码例子\comparator\ISE\comparator\comparator_pad.txt
Verilog源码例子\comparator\ISE\comparator\comparator_vhdl.prj
Verilog源码例子\comparator\ISE\comparator\xst\work\hdllib.ref
Verilog源码例子\comparator\ISE\comparator\xst\work\vlg6C\comparator.bin
Verilog源码例子\comparator\ISE\comparator\xst\work\vlg6C
Verilog源码例子\comparator\ISE\comparator\xst\work
Verilog源码例子\comparator\ISE\comparator\xst
Verilog源码例子\comparator\ISE\comparator\_ngo\netlist.lst
Verilog源码例子\comparator\ISE\comparator\_ngo
Verilog源码例子\comparator\ISE\comparator\__projnav\bitgen.rsp
Verilog源码例子\comparator\ISE\comparator\__projnav\comparator.gfl
Verilog源码例子\comparator\ISE\comparator\__projnav\comparator.xst
Verilog源码例子\comparator\ISE\comparator\__projnav\comparator_flowplus.gfl
Verilog源码例子\comparator\ISE\comparator\__projnav\comparator_ncdTOut_tcl.rsp
Verilog源码例子\comparator\ISE\comparator\__projnav\ednTOngd_tcl.rsp
Verilog源码例子\comparator\ISE\comparator\__projnav\map.log
Verilog源码例子\comparator\ISE\comparator\__projnav\nc1TOncd_tcl.rsp
Verilog源码例子\comparator\ISE\comparator\__projnav\par.log
Verilog源码例子\comparator\ISE\comparator\__projnav\parentAssignPackagePinsApp_tcl.rsp
Verilog源码例子\comparator\ISE\comparator\__projnav\posttrc.log
Verilog源码例子\comparator\ISE\comparator\__projnav\runXst_tcl.rsp
Verilog源码例子\comparator\ISE\comparator\__projnav
Verilog源码例子\comparator\ISE\comparator\__projnav.log
Verilog源码例子\comparator\ISE\comparator
Verilog源码例子\comparator\ISE
Verilog源码例子\comparator\modelsim\comparator.cr.mti
Verilog源码例子\comparator\modelsim\comparator.mpf
Verilog源码例子\comparator\modelsim\vsim.wlf
Verilog源码例子\comparator\modelsim\work\comparator\verilog.asm
Verilog源码例子\comparator\modelsim\work\comparator\_primary.dat
Verilog源码例子\comparator\modelsim\work\comparator\_primary.vhd
Verilog源码例子\comparator\modelsim\work\comparator
Verilog源码例子\comparator\modelsim\work\tb_comparator\verilog.asm
Verilog源码例子\comparator\modelsim\work\tb_comparator\_primary.dat
Verilog源码例子\comparator\modelsim\work\tb_comparator\_primary.vhd
Verilog源码例子\comparator\modelsim\work\tb_comparator
Verilog源码例子\comparator\modelsim\work\_info
Verilog源码例子\comparator\modelsim\work
Verilog源码例子\comparator\modelsim
Verilog源码例子\comparator\rtl\comparator.v
Verilog源码例子\comparator\rtl\tb_comparator.v
Verilog源码例子\comparator\rtl
Verilog源码例子\comparator
Verilog源码例子\counter16\ISE\counter16_top.v\.untf
Verilog源码例子\counter16\ISE\counter16_top.v\automake.log
Verilog源码例子\counter16\ISE\counter16_top.v\bitgen.ut
Verilog源码例子\counter16\ISE\counter16_top.v\counter16.v
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.bgn
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.bit
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.bld
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.cmd_log
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.dhp
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.drc
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.lfp
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.lso
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.mrp
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.nc1
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ncd
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ngc
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ngd
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ngm
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ngr
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.npl
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.pad
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.pad_txt
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.par
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.pcf
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.placed_ncd_tracker
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.prj
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.routed_ncd_tracker
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.stx
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.syr
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.twr
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.twx
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ucf
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ucf.untf
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.ut
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.v
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top.xpi
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top_map.ncd
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top_map.ngm
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top_pad.csv
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top_pad.txt
Verilog源码例子\counter16\ISE\counter16_top.v\counter16_top_vhdl.prj
Verilog源码例子\counter16\ISE\counter16_top.v\xst\work\hdllib.ref
Verilog源码例子\counter16\ISE\counter16_top.v\xst\work\vlg3B\counter16.bin
Verilog源码例子\counter16\ISE\counter16_top.v\xst\work\vlg3B
Verilog源码例子\counter16\ISE\counter16_top.v\xst\work\vlg5D\counter16_top.bin
Verilog源码例子\counter16\ISE\counter16_top.v\xst\work\vlg5D
Verilog源码例子\counter16\ISE\counter16_top.v\xst\work
Verilog源码例子\counter16\ISE\counter16_top.v\xst
Verilog源码例子\counter16\ISE\counter16_top.v\_ngo\netlist.lst
Verilog源码例子\counter16\ISE\counter16_top.v\_ngo
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\bitgen.rsp
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\counter16_top.gfl
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\counter16_top.xst
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\counter16_top_flowplus.gfl
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\counter16_top_ncdTOut_tcl.rsp
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\ednTOngd_tcl.rsp
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\map.log
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\nc1TOncd_tcl.rsp
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\par.log
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\parentAssignPackagePinsApp_tcl.rsp
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\posttrc.log
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav\runXst_tcl.rsp
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav
Verilog源码例子\counter16\ISE\counter16_top.v\__projnav.log
Verilog源码例子\counter16\ISE\counter16_top.v
Verilog源码例子\counter16\ISE
Verilog源码例子\counter16\modelsim\counter16.cr.mti
Verilog源码例子\counter16\modelsim\counter16.mpf
Verilog源码例子\counter16\modelsim\transcript
Verilog源码例子\counter16\modelsim\vsim.wlf
Verilog源码例子\counter16\modelsim\work\counter16\verilog.asm
Verilog源码例子\counter16\modelsim\work\counter16\_primary.dat
Verilog源码例子\counter16\modelsim\work\counter16\_primary.vhd
Verilog源码例子\counter16\modelsim\work\counter16
Verilog源码例子\counter16\modelsim\work\tb_counter16\verilog.asm
Verilog源码例子\counter16\modelsim\work\tb_counter16\_primary.dat
Verilog源码例子\counter16\modelsim\work\tb_counter16\_primary.vhd
Verilog源码例子\counter16\modelsim\work\tb_counter16
Verilog源码例子\counter16\modelsim\work\_info
Verilog源码例子\counter16\modelsim\work
Verilog源码例子\counter16\modelsim
Verilog源码例子\counter16\rtl\counter16.v
Verilog源码例子\counter16\rtl\counter16_top.v
Verilog源码例子\counter16\rtl\tb_counter16.v
Verilog源码例子\counter16\rtl
Verilog源码例子\counter16
Verilog源码例子\decoder\ISE\decoder\.untf
Verilog源码例子\decoder\ISE\decoder\automake.log
Verilog源码例子\decoder\ISE\decoder\bitgen.ut
Verilog源码例子\decoder\ISE\decoder\decoder.bgn
Verilog源码例子\decoder\ISE\decoder\decoder.bit
Verilog源码例子\decoder\ISE\decoder\decoder.bld
Verilog源码例子\decoder\ISE\decoder\decoder.cmd_log
Verilog源码例子\decoder\ISE\decoder\decoder.dhp
Verilog源码例子\decoder\ISE\decoder\decoder.drc
Verilog源码例子\decoder\ISE\decoder\decoder.lfp
Verilog源码例子\decoder\ISE\decoder\decoder.lso
Verilog源码例子\decoder\ISE\decoder\decoder.mrp
Verilog源码例子\decoder\ISE\decoder\decoder.nc1
Verilog源码例子\decoder\ISE\decoder\decoder.ncd
Verilog源码例子\decoder\ISE\decoder\decoder.ngc
Verilog源码例子\decoder\ISE\decoder\decoder.ngd
Verilog源码例子\decoder\ISE\decoder\decoder.ngm
Verilog源码例子\decoder\ISE\decoder\decoder.ngr
Verilog源码例子\decoder\ISE\decoder\decoder.npl
Verilog源码例子\decoder\ISE\decoder\decoder.pad
Verilog源码例子\decoder\ISE\decoder\decoder.pad_txt
Verilog源码例子\decoder\ISE\decoder\decoder.par
Verilog源码例子\decoder\ISE\decoder\decoder.pcf
Verilog源码例子\decoder\ISE\decoder\decoder.placed_ncd_tracker
Verilog源码例子\decoder\ISE\decoder\decoder.prj
Verilog源码例子\decoder\ISE\decoder\decoder.routed_ncd_tracker
Verilog源码例子\decoder\ISE\decoder\decoder.stx
Verilog源码例子\decoder\ISE\decoder\decoder.syr
Verilog源码例子\decoder\ISE\decoder\decoder.twr
Verilog源码例子\decoder\ISE\decoder\decoder.twx
Verilog源码例子\decoder\ISE\decoder\decoder.ucf
Verilog源码例子\decoder\ISE\decoder\decoder.ucf.untf
Verilog源码例子\decoder\ISE\decoder\decoder.ut
Verilog源码例子\decoder\ISE\decoder\decoder.v
Verilog源码例子\decoder\ISE\decoder\decoder.xpi
Verilog源码例子\decoder\ISE\decoder\decoder_map.ncd
Verilog源码例子\decoder\ISE\decoder\decoder_map.ngm
Verilog源码例子\decoder\ISE\decoder\decoder_pad.csv
Verilog源码例子\decoder\ISE\decoder\decoder_pad.txt
Verilog源码例子\decoder\ISE\decoder\decoder_vhdl.prj
Verilog源码例子\decoder\ISE\decoder\xst\work\hdllib.ref
Verilog源码例子\decoder\ISE\decoder\xst\work\vlg02\decoder.bin
Verilog源码例子\decoder\ISE\decoder\xst\work\vlg02
Verilog源码例子\decoder\ISE\decoder\xst\work
Verilog源码例子\decoder\ISE\decoder\xst
Verilog源码例子\decoder\ISE\decoder\_ngo\netlist.lst
Verilog源码例子\decoder\ISE\decoder\_ngo
Verilog源码例子\decoder\ISE\decoder\_pace.ucf
Verilog源码例子\decoder\ISE\decoder\__projnav\bitgen.rsp
Verilog源码例子\decoder\ISE\decoder\__projnav\decoder.gfl
Verilog源码例子\decoder\ISE\decoder\__projnav\decoder.xst
Verilog源码例子\decoder\ISE\decoder\__projnav\decoder_flowplus.gfl
Verilog源码例子\decoder\ISE\decoder\__projnav\decoder_ncdTOut_tcl.rsp
Verilog源码例子\decoder\ISE\decoder\__projnav\ednTOngd_tcl.rsp
Verilog源码例子\decoder\ISE\decoder\__projnav\map.log
Verilog源码例子\decoder\ISE\decoder\__projnav\nc1TOncd_tcl.rsp
Verilog源码例子\decoder\ISE\decoder\__projnav\par.log
Verilog源码例子\decoder\ISE\decoder\__projnav\parentAssignPackagePinsApp_tcl.rsp
Verilog源码例子\decoder\ISE\decoder\__projnav\posttrc.log
Verilog源码例子\decoder\ISE\decoder\__projnav\runXst_tcl.rsp
Verilog源码例子\decoder\ISE\decoder\__projnav
Verilog源码例子\decoder\ISE\decoder\__projnav.log
Verilog源码例子\decoder\ISE\decoder
Verilog源码例子\decoder\ISE
Verilog源码例子\decoder\modelsim\decoder.cr.mti
Verilog源码例子\decoder\modelsim\decoder.mpf
Verilog源码例子\decoder\modelsim\vsim.wlf
Verilog源码例子\decoder\modelsim\work\decoder\verilog.asm
Verilog源码例子\decoder\modelsim\work\decoder\_primary.dat
Verilog源码例子\decoder\modelsim\work\decoder\_primary.vhd
Verilog源码例子\decoder\modelsim\work\decoder
Verilog源码例子\decoder\modelsim\work\tb_decoder\verilog.asm
Verilog源码例子\decoder\modelsim\work\tb_decoder\_primary.dat
Verilog源码例子\decoder\modelsim\work\tb_decoder\_primary.vhd
Verilog源码例子\decoder\modelsim\work\tb_decoder
Verilog源码例子\decoder\modelsim\work\_info
Verilog源码例子\decoder\modelsim\work
Verilog源码例子\decoder\modelsim
Verilog源码例子\decoder\rtl\decoder.v
Verilog源码例子\decoder\rtl\tb_decoder.v
Verilog源码例子\decoder\rtl
Verilog源码例子\decoder
Verilog源码例子\iic\ISE\iic\.untf
Verilog源码例子\iic\ISE\iic\automake.log
Verilog源码例子\iic\ISE\iic\bitgen.ut
Verilog源码例子\iic\ISE\iic\coregen.log
Verilog源码例子\iic\ISE\iic\coregen.prj
Verilog源码例子\iic\ISE\iic\i2c.bgn
Verilog源码例子\iic\ISE\iic\i2c.bit
Verilog源码例子\iic\ISE\iic\i2c.bld
Verilog源码例子\iic\ISE\iic\i2c.cmd_log
Verilog源码例子\iic\ISE\iic\i2c.drc
Verilog源码例子\iic\ISE\iic\i2c.lfp
Verilog源码例子\iic\ISE\iic\i2c.lso
Verilog源码例子\iic\ISE\iic\i2c.mrp
Verilog源码例子\iic\ISE\iic\i2c.nc1
Verilog源码例子\iic\ISE\iic\i2c.ncd
Verilog源码例子\iic\ISE\iic\i2c.ngc
Verilog源码例子\iic\ISE\iic\i2c.ngd
Verilog源码例子\iic\ISE\iic\i2c.ngm
Verilog源码例子\iic\ISE\iic\i2c.ngr
Verilog源码例子\iic\ISE\iic\i2c.pad
Verilog源码例子\iic\ISE\iic\i2c.pad_txt
Verilog源码例子\iic\ISE\iic\i2c.par
Verilog源码例子\iic\ISE\iic\i2c.pcf
Verilog源码例子\iic\ISE\iic\i2c.placed_ncd_tracker
Verilog源码例子\iic\ISE\iic\i2c.prj
Verilog源码例子\iic\ISE\iic\i2c.routed_ncd_tracker
Verilog源码例子\iic\ISE\iic\i2c.stx
Verilog源码例子\iic\ISE\iic\i2c.syr
Verilog源码例子\iic\ISE\iic\i2c.twr
Verilog源码例子\iic\ISE\iic\i2c.twx
Verilog源码例子\iic\ISE\iic\i2c.ucf
Verilog源码例子\iic\ISE\iic\i2c.ucf.untf
Verilog源码例子\iic\ISE\iic\i2c.ut
Verilog源码例子\iic\ISE\iic\i2c.v
Verilog源码例子\iic\ISE\iic\i2c.xpi
Verilog源码例子\iic\ISE\iic\i2c_clk.v
Verilog源码例子\iic\ISE\iic\i2c_last_par.ncd
Verilog源码例子\iic\ISE\iic\i2c_map.ncd
Verilog源码例子\iic\ISE\iic\i2c_map.ngm
Verilog源码例子\iic\ISE\iic\i2c_pad.csv
Verilog源码例子\iic\ISE\iic\i2c_pad.txt
Verilog源码例子\iic\ISE\iic\i2c_st.v
Verilog源码例子\iic\ISE\iic\i2c_st.v.bak
Verilog源码例子\iic\ISE\iic\i2c_vhdl.prj
Verilog源码例子\iic\ISE\iic\iic.dhp
Verilog源码例子\iic\ISE\iic\iic.npl
Verilog源码例子\iic\ISE\iic\xst\work\hdllib.ref
Verilog源码例子\iic\ISE\iic\xst\work\vlg1E\i2c.bin
Verilog源码例子\iic\ISE\iic\xst\work\vlg1E
Verilog源码例子\iic\ISE\iic\xst\work\vlg20\i2c_st.bin
Verilog源码例子\iic\ISE\iic\xst\work\vlg20
Verilog源码例子\iic\ISE\iic\xst\work\vlg53\i2c_clk.bin
Verilog源码例子\iic\ISE\iic\xst\work\vlg53
Verilog源码例子\iic\ISE\iic\xst\work
Verilog源码例子\iic\ISE\iic\xst
Verilog源码例子\iic\ISE\iic\_impact.cmd
Verilog源码例子\iic\ISE\iic\_impact.log
Verilog源码例子\iic\ISE\iic\_ngo\netlist.lst
Verilog源码例子\iic\ISE\iic\_ngo
Verilog源码例子\iic\ISE\iic\__projnav\bitgen.rsp
Verilog源码例子\iic\ISE\iic\__projnav\coregen.rsp
Verilog源码例子\iic\ISE\iic\__projnav\ednTOngd_tcl.rsp
Verilog源码例子\iic\ISE\iic\__projnav\i2c.xst
Verilog源码例子\iic\ISE\iic\__projnav\i2c_ncdTOut_tcl.rsp
Verilog源码例子\iic\ISE\iic\__projnav\iic.gfl
Verilog源码例子\iic\ISE\iic\__projnav\iic_flowplus.gfl
Verilog源码例子\iic\ISE\iic\__projnav\map.log
Verilog源码例子\iic\ISE\iic\__projnav\nc1TOncd_tcl.rsp
Verilog源码例子\iic\ISE\iic\__projnav\par.log
Verilog源码例子\iic\ISE\iic\__projnav\parentAssignPackagePinsApp_tcl.rsp
Verilog源码例子\iic\ISE\iic\__projnav\posttrc.log
Verilog源码例子\iic\ISE\iic\__projnav\runXst_tcl.rsp
Verilog源码例子\iic\ISE\iic\__projnav
Verilog源码例子\iic\ISE\iic\__projnav.log
Verilog源码例子\iic\ISE\iic
Verilog源码例子\iic\ISE
Verilog源码例子\iic\RTL\BACK\clk_rst.v
Verilog源码例子\iic\RTL\BACK\i2c.v
Verilog源码例子\iic\RTL\BACK\i2c.v.bak
Verilog源码例子\iic\RTL\BACK\i2c_clk.v
Verilog源码例子\iic\RTL\BACK\i2c_clk.v.bak
Verilog源码例子\iic\RTL\BACK\i2c_rreg.v
Verilog源码例子\iic\RTL\BACK\i2c_st.v
Verilog源码例子\iic\RTL\BACK\i2c_st.v.bak
Verilog源码例子\iic\RTL\BACK\i2c_tbuf.v
Verilog源码例子\iic\RTL\BACK\i2c_tbuf.v.bak
Verilog源码例子\iic\RTL\BACK\i2c_wreg.v
Verilog源码例子\iic\RTL\BACK
Verilog源码例子\iic\RTL\i2c.v
Verilog源码例子\iic\RTL\i2c.v.bak
Verilog源码例子\iic\RTL\i2c_clk.v
Verilog源码例子\iic\RTL\i2c_st.bak
Verilog源码例子\iic\RTL\i2c_st.v
Verilog源码例子\iic\RTL
Verilog源码例子\iic
Verilog源码例子\lcm\ISE\LCM\.untf
Verilog源码例子\lcm\ISE\LCM\automake.log
Verilog源码例子\lcm\ISE\LCM\bitgen.ut
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.bgn
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.bit
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.bld
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.cmd_log
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.drc
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.lfp
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.lso
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.mrp
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.nc1
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ncd
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngc
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngd
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngm
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngr
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.pad
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.pad_txt
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.par
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.pcf
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.placed_ncd_tracker
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.prj
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.routed_ncd_tracker
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.stx
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.syr
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.twr
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.twx
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ucf
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ucf.untf
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ut
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.v
Verilog源码例子\lcm\ISE\LCM\fpga_lcm.xpi
Verilog源码例子\lcm\ISE\LCM\fpga_lcm_last_par.ncd
Verilog源码例子\lcm\ISE\LCM\fpga_lcm_map.ncd
Verilog源码例子\lcm\ISE\LCM\fpga_lcm_map.ngm
Verilog源码例子\lcm\ISE\LCM\fpga_lcm_pad.csv
Verilog源码例子\lcm\ISE\LCM\fpga_lcm_pad.txt
Verilog源码例子\lcm\ISE\LCM\fpga_lcm_vhdl.prj
Verilog源码例子\lcm\ISE\LCM\LCM.dhp
Verilog源码例子\lcm\ISE\LCM\LCM.npl
Verilog源码例子\lcm\ISE\LCM\lcm.v
Verilog源码例子\lcm\ISE\LCM\rom_32x8.bgn
Verilog源码例子\lcm\ISE\LCM\rom_32x8.bit
Verilog源码例子\lcm\ISE\LCM\rom_32x8.bld
Verilog源码例子\lcm\ISE\LCM\rom_32x8.cmd_log
Verilog源码例子\lcm\ISE\LCM\rom_32x8.drc
Verilog源码例子\lcm\ISE\LCM\rom_32x8.lso
Verilog源码例子\lcm\ISE\LCM\rom_32x8.mrp
Verilog源码例子\lcm\ISE\LCM\rom_32x8.nc1
Verilog源码例子\lcm\ISE\LCM\rom_32x8.ncd
Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngc
Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngd
Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngm
Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngr
Verilog源码例子\lcm\ISE\LCM\rom_32x8.pad
Verilog源码例子\lcm\ISE\LCM\rom_32x8.pad_txt
Verilog源码例子\lcm\ISE\LCM\rom_32x8.par
Verilog源码例子\lcm\ISE\LCM\rom_32x8.pcf
Verilog源码例子\lcm\ISE\LCM\rom_32x8.placed_ncd_tracker
Verilog源码例子\lcm\ISE\LCM\rom_32x8.prj
Verilog源码例子\lcm\ISE\LCM\rom_32x8.routed_ncd_tracker
Verilog源码例子\lcm\ISE\LCM\rom_32x8.stx
Verilog源码例子\lcm\ISE\LCM\rom_32x8.syr
Verilog源码例子\lcm\ISE\LCM\rom_32x8.twr
Verilog源码例子\lcm\ISE\LCM\rom_32x8.twx
Verilog源码例子\lcm\ISE\LCM\rom_32x8.ucf
Verilog源码例子\lcm\ISE\LCM\rom_32x8.ut
Verilog源码例子\lcm\ISE\LCM\rom_32x8.v
Verilog源码例子\lcm\ISE\LCM\rom_32x8.xpi
Verilog源码例子\lcm\ISE\LCM\rom_32x8_map.ncd
Verilog源码例子\lcm\ISE\LCM\rom_32x8_map.ngm
Verilog源码例子\lcm\ISE\LCM\rom_32x8_pad.csv
Verilog源码例子\lcm\ISE\LCM\rom_32x8_pad.txt
Verilog源码例子\lcm\ISE\LCM\rom_32x8_vhdl.prj
Verilog源码例子\lcm\ISE\LCM\xst\work\hdllib.ref
Verilog源码例子\lcm\ISE\LCM\xst\work\vlg4A\rom_32x8.bin
Verilog源码例子\lcm\ISE\LCM\xst\work\vlg4A
Verilog源码例子\lcm\ISE\LCM\xst\work\vlg4D\fpga_lcm.bin
Verilog源码例子\lcm\ISE\LCM\xst\work\vlg4D
Verilog源码例子\lcm\ISE\LCM\xst\work\vlg68\lcm.bin
Verilog源码例子\lcm\ISE\LCM\xst\work\vlg68
Verilog源码例子\lcm\ISE\LCM\xst\work
Verilog源码例子\lcm\ISE\LCM\xst
Verilog源码例子\lcm\ISE\LCM\_ngo\netlist.lst
Verilog源码例子\lcm\ISE\LCM\_ngo
Verilog源码例子\lcm\ISE\LCM\__projnav\ad.gfl
Verilog源码例子\lcm\ISE\LCM\__projnav\bitgen.rsp
Verilog源码例子\lcm\ISE\LCM\__projnav\ednTOngd_tcl.rsp
Verilog源码例子\lcm\ISE\LCM\__projnav\fpga_lcm.xst
Verilog源码例子\lcm\ISE\LCM\__projnav\fpga_lcm_ncdTOut_tcl.rsp
Verilog源码例子\lcm\ISE\LCM\__projnav\LCM.gfl
Verilog源码例子\lcm\ISE\LCM\__projnav\LCM_flowplus.gfl
Verilog源码例子\lcm\ISE\LCM\__projnav\map.log
Verilog源码例子\lcm\ISE\LCM\__projnav\nc1TOncd_tcl.rsp
Verilog源码例子\lcm\ISE\LCM\__projnav\par.log
Verilog源码例子\lcm\ISE\LCM\__projnav\parentAssignPackagePinsApp_tcl.rsp
Verilog源码例子\lcm\ISE\LCM\__projnav\posttrc.log
Verilog源码例子\lcm\ISE\LCM\__projnav\rom_32x8.xst
Verilog源码例子\lcm\ISE\LCM\__projnav\rom_32x8_ncdTOut_tcl.rsp
Verilog源码例子\lcm\ISE\LCM\__projnav\runXst_tcl.rsp
Verilog源码例子\lcm\ISE\LCM\__projnav
Verilog源码例子\lcm\ISE\LCM\__projnav.log
Verilog源码例子\lcm\ISE\LCM
Verilog源码例子\lcm\ISE
Verilog源码例子\lcm\RTL\fpga_lcm.v
Verilog源码例子\lcm\RTL\lcm.v
Verilog源码例子\lcm\RTL\rom_32x8.v
Verilog源码例子\lcm\RTL
Verilog源码例子\lcm
Verilog源码例子\myadder\maadder.v
Verilog源码例子\myadder\tb_myadder.v
Verilog源码例子\myadder\transcript
Verilog源码例子\myadder
Verilog源码例子\rs232\ISE\rs23240x\automake.log
Verilog源码例子\rs232\ISE\rs23240x\bitgen.ut
Verilog源码例子\rs232\ISE\rs23240x\diag.v
Verilog源码例子\rs232\ISE\rs23240x\fpga_40rs232.bgn
Verilog源码例子\rs232\ISE\rs23240x\fpga_40rs232.bit
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.bld
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.cmd_log
Verilog源码例子\rs232\ISE\rs23240x\fpga_40rs232.drc
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.lso
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.mrp
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.nc1
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ncd
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngc
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngd
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngm
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngr
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.pad
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.pad_txt
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.par
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.pcf
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.placed_ncd_tracker
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.prj
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.routed_ncd_tracker
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.stx
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.syr
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.twr
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.twx
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ut
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.xpi
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_last_par.ncd
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_map.ncd
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_map.ngm
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_pad.csv
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_pad.txt
Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_vhdl.prj
Verilog源码例子\rs232\ISE\rs23240x\fpga_40XRS232.ucf
Verilog源码例子\rs232\ISE\rs23240x\fpga_40XRS232.ucf.untf
Verilog源码例子\rs232\ISE\rs23240x\fpga_40XRS232.v
Verilog源码例子\rs232\ISE\rs23240x\rs23240x.dhp
Verilog源码例子\rs232\ISE\rs23240x\rs23240x.npl
Verilog源码例子\rs232\ISE\rs23240x\serial.v
Verilog源码例子\rs232\ISE\rs23240x\xst\work\hdllib.ref
Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg20\serial.bin
Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg20
Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg25\fpga_40RS232.bin
Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg25
Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg61\diag.bin
Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg61
Verilog源码例子\rs232\ISE\rs23240x\xst\work
Verilog源码例子\rs232\ISE\rs23240x\xst
Verilog源码例子\rs232\ISE\rs23240x\_ngo\netlist.lst
Verilog源码例子\rs232\ISE\rs23240x\_ngo
Verilog源码例子\rs232\ISE\rs23240x\__projnav\bitgen.rsp
Verilog源码例子\rs232\ISE\rs23240x\__projnav\ednTOngd_tcl.rsp
Verilog源码例子\rs232\ISE\rs23240x\__projnav\fpga_40RS232.xst
Verilog源码例子\rs232\ISE\rs23240x\__projnav\fpga_40RS232_ncdTOut_tcl.rsp
Verilog源码例子\rs232\ISE\rs23240x\__projnav\map.log
Verilog源码例子\rs232\ISE\rs23240x\__projnav\nc1TOncd_tcl.rsp
Verilog源码例子\rs232\ISE\rs23240x\__projnav\par.log
Verilog源码例子\rs232\ISE\rs23240x\__projnav\posttrc.log
Verilog源码例子\rs232\ISE\rs23240x\__projnav\rs23240x.gfl
Verilog源码例子\rs232\ISE\rs23240x\__projnav\rs23240x_flowplus.gfl
Verilog源码例子\rs232\ISE\rs23240x\__projnav\runXst_tcl.rsp
Verilog源码例子\rs232\ISE\rs23240x\__projnav
Verilog源码例子\rs232\ISE\rs23240x\__projnav.log
Verilog源码例子\rs232\ISE\rs23240x
Verilog源码例子\rs232\ISE
Verilog源码例子\rs232\rtl\diag.v
Verilog源码例子\rs232\rtl\fpga_40XRS232.ucf
Verilog源码例子\rs232\rtl\fpga_40XRS232.ucf.bak
Verilog源码例子\rs232\rtl\fpga_40XRS232.v
Verilog源码例子\rs232\rtl\fpga_40XRS232.v.bak
Verilog源码例子\rs232\rtl\serial.v
Verilog源码例子\rs232\rtl
Verilog源码例子\rs232
Verilog源码例子\串并转换\S2P.v
Verilog源码例子\串并转换\S2P.v.bak
Verilog源码例子\串并转换\tb_s2p.v
Verilog源码例子\串并转换
Verilog源码例子\本文件夹例子说明.doc
Verilog源码例子