Using FPGA, VHDL realize the UART core, quartusII complete projects, practical

Packet : 37724075uart.rar filelist
Uart\baud.bsf
Uart\baud.vhd
Uart\baud.vhd.bak
Uart\db\prev_cmp_Uart.qmsg
Uart\db\Uart.(0).cnf.cdb
Uart\db\Uart.(0).cnf.hdb
Uart\db\Uart.(1).cnf.cdb
Uart\db\Uart.(1).cnf.hdb
Uart\db\Uart.(2).cnf.cdb
Uart\db\Uart.(2).cnf.hdb
Uart\db\Uart.(3).cnf.cdb
Uart\db\Uart.(3).cnf.hdb
Uart\db\Uart.asm.qmsg
Uart\db\Uart.asm_labs.ddb
Uart\db\Uart.cbx.xml
Uart\db\Uart.cmp.bpm
Uart\db\Uart.cmp.cdb
Uart\db\Uart.cmp.ecobp
Uart\db\Uart.cmp.hdb
Uart\db\Uart.cmp.logdb
Uart\db\Uart.cmp.rdb
Uart\db\Uart.cmp.tdb
Uart\db\Uart.cmp0.ddb
Uart\db\Uart.cmp_bb.cdb
Uart\db\Uart.cmp_bb.hdb
Uart\db\Uart.cmp_bb.logdb
Uart\db\Uart.cmp_bb.rcf
Uart\db\Uart.dbp
Uart\db\Uart.db_info
Uart\db\Uart.eco.cdb
Uart\db\Uart.fit.qmsg
Uart\db\Uart.hier_info
Uart\db\Uart.hif
Uart\db\Uart.map.bpm
Uart\db\Uart.map.cdb
Uart\db\Uart.map.ecobp
Uart\db\Uart.map.hdb
Uart\db\Uart.map.logdb
Uart\db\Uart.map.qmsg
Uart\db\Uart.map_bb.cdb
Uart\db\Uart.map_bb.hdb
Uart\db\Uart.map_bb.logdb
Uart\db\Uart.pre_map.cdb
Uart\db\Uart.pre_map.hdb
Uart\db\Uart.psp
Uart\db\Uart.pss
Uart\db\Uart.rtlv.hdb
Uart\db\Uart.rtlv_sg.cdb
Uart\db\Uart.rtlv_sg_swap.cdb
Uart\db\Uart.sgdiff.cdb
Uart\db\Uart.sgdiff.hdb
Uart\db\Uart.signalprobe.cdb
Uart\db\Uart.sld_design_entry.sci
Uart\db\Uart.sld_design_entry_dsc.sci
Uart\db\Uart.smp_dump.txt
Uart\db\Uart.syn_hier_info
Uart\db\Uart.tan.qmsg
Uart\db\Uart.tis_db_list.ddb
Uart\db
Uart\reciever.bsf
Uart\reciever.vhd
Uart\transfer.bsf
Uart\transfer.vhd
Uart\Uart.asm.rpt
Uart\Uart.bdf
Uart\Uart.done
Uart\Uart.fit.rpt
Uart\Uart.fit.smsg
Uart\Uart.fit.summary
Uart\Uart.flow.rpt
Uart\Uart.map.rpt
Uart\Uart.map.summary
Uart\Uart.pin
Uart\Uart.pof
Uart\Uart.qpf
Uart\Uart.qsf
Uart\Uart.qws
Uart\Uart.sof
Uart\Uart.tan.rpt
Uart\Uart.tan.summary
Uart

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