Use verilog as CPU design language to implement the CPU of the five-stage pipeline of single-data channel. There are 32 common registers, one program counter PC, one FLAG register FLAG, one STACK register STACK. Memory addressing granularity is byte. The data store is aligned with a 32-bit character. Using the 32-bit fixed-length instruction format, the Load/Store structure is adopted, and the ALU instruction adopts the three-address format. Support signed and unsigned integer add, subtract, multiply, divide, and support floating-point number add, subtract, multiply and divide four kinds of operation, support and, or, xor, the four kinds of logic operation, support left, logic shift right, logic arithmetic moves to the right, loop moves to the right four shift operations, support the Load/Store operations, support the address/number immediately Load operation, support the unconditional transfer and zero transfer, transfer of non-zero, unsigned & gt; Transfer, unsigned < Transfer, symbol > Transfer, symbol < Transfer of other conditions.

Packet : 3970994cpu.rar filelist
add.v
alu.v
condcontrol.v
control.v
d_8.v
d_8_1.v
d_8_1_bb.v
d_8_bb.v
d_32.v
d_32_bb.v
d_32_inst.v
datapath.v
div.v
fpu_arch.v
func_lib.v
in_32.v
in_32_bb.v
in_32_inst.v
instruction_32.v
instruction_32_1.v
instruction_32_1_bb.v
instruction_32_bb.v
instruction_32_inst.v
mul.v
pc.v
regfile.v
ss.v
ss_bb.v
ss_syn.v
stack.v
sub.v

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