VGA display on the VHDL source code, in line with the relevant vga timing is an important reference for you.

Packet : 5956454vga_display.rar filelist
vga_display\db\vga.(0).cnf.cdb
vga_display\db\vga.(0).cnf.hdb
vga_display\db\vga.asm.qmsg
vga_display\db\vga.asm_labs.ddb
vga_display\db\vga.cbx.xml
vga_display\db\vga.cmp.cdb
vga_display\db\vga.cmp.hdb
vga_display\db\vga.cmp.kpt
vga_display\db\vga.cmp.logdb
vga_display\db\vga.cmp.rdb
vga_display\db\vga.cmp.tdb
vga_display\db\vga.cmp0.ddb
vga_display\db\vga.cmp2.ddb
vga_display\db\vga.dbp
vga_display\db\vga.db_info
vga_display\db\vga.eco.cdb
vga_display\db\vga.eda.qmsg
vga_display\db\vga.fit.qmsg
vga_display\db\vga.hier_info
vga_display\db\vga.hif
vga_display\db\vga.map.cdb
vga_display\db\vga.map.hdb
vga_display\db\vga.map.logdb
vga_display\db\vga.map.qmsg
vga_display\db\vga.pre_map.cdb
vga_display\db\vga.pre_map.hdb
vga_display\db\vga.psp
vga_display\db\vga.pss
vga_display\db\vga.rtlv.hdb
vga_display\db\vga.rtlv_sg.cdb
vga_display\db\vga.rtlv_sg_swap.cdb
vga_display\db\vga.sgdiff.cdb
vga_display\db\vga.sgdiff.hdb
vga_display\db\vga.signalprobe.cdb
vga_display\db\vga.sld_design_entry.sci
vga_display\db\vga.sld_design_entry_dsc.sci
vga_display\db\vga.syn_hier_info
vga_display\db\vga.tan.qmsg
vga_display\simulation\modelsim\vga.vo
vga_display\simulation\modelsim\vga_modelsim.xrf
vga_display\simulation\modelsim\vga_v.sdo
vga_display\vga.asm.rpt
vga_display\vga.cdf
vga_display\vga.done
vga_display\vga.eda.rpt
vga_display\vga.fit.rpt
vga_display\vga.fit.smsg
vga_display\vga.fit.summary
vga_display\vga.flow.rpt
vga_display\vga.map.rpt
vga_display\vga.map.summary
vga_display\vga.pin
vga_display\vga.pof
vga_display\vga.qpf
vga_display\vga.qsf
vga_display\vga.qws
vga_display\vga.sof
vga_display\vga.tan.rpt
vga_display\vga.tan.summary
vga_display\vga.v
vga_display\simulation\modelsim
vga_display\db
vga_display\simulation
vga_display

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