Introduction - If you have any usage issues, please Google them yourself
crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Packet : 33753166crc16_ccitt.rar filelist
crc16_ccitt\CRC16_D8_m.v
crc16_ccitt\CRC16_D8_m_tb.v
crc16_ccitt\crc_table.c
crc16_ccitt\crc_table_1.c
crc16_ccitt