VHDL language experimental digital clock function, can be manually adjusted, the set-up à bell, etc.

Packet : 17869337shiyan14.rar filelist
shiyan14\DAC.vhd
shiyan14\DAC.qpf
shiyan14\DAC.qsf
shiyan14\DAC.map.rpt
shiyan14\DAC.flow.rpt
shiyan14\DAC.map.summary
shiyan14\DAC.pin
shiyan14\DAC.fit.rpt
shiyan14\DAC.fit.summary
shiyan14\DAC.sof
shiyan14\DAC.pof
shiyan14\DAC.asm.rpt
shiyan14\DAC.tan.summary
shiyan14\DAC.tan.rpt
shiyan14\DAC.done
shiyan14\DAC.vwf
shiyan14\DAC.sim.rpt
shiyan14\DAC.cdf
shiyan14\DAC.qws
shiyan14\db\DAC.db_info
shiyan14\db\DAC.sld_design_entry.sci
shiyan14\db\DAC.rtlv_sg.cdb
shiyan14\db\DAC.cmp.rdb
shiyan14\db\DAC.rtlv_sg_swap.cdb
shiyan14\db\DAC.map.qmsg
shiyan14\db\DAC.eco.cdb
shiyan14\db\DAC.rtlv.hdb
shiyan14\db\DAC.map.logdb
shiyan14\db\DAC.cbx.xml
shiyan14\db\DAC.hif
shiyan14\db\DAC.(0).cnf.cdb
shiyan14\db\DAC.(0).cnf.hdb
shiyan14\db\DAC.hier_info
shiyan14\db\DAC.pre_map.hdb
shiyan14\db\DAC.pre_map.cdb
shiyan14\db\DAC.sgdiff.cdb
shiyan14\db\DAC.sgdiff.hdb
shiyan14\db\DAC.sld_design_entry_dsc.sci
shiyan14\db\DAC.psp
shiyan14\db\DAC.dbp
shiyan14\db\DAC.(1).cnf.cdb
shiyan14\db\DAC.(1).cnf.hdb
shiyan14\db\DAC.(2).cnf.cdb
shiyan14\db\DAC.(2).cnf.hdb
shiyan14\db\DAC.(3).cnf.cdb
shiyan14\db\DAC.(3).cnf.hdb
shiyan14\db\DAC.(4).cnf.cdb
shiyan14\db\DAC.(4).cnf.hdb
shiyan14\db\DAC.(5).cnf.cdb
shiyan14\db\DAC.(5).cnf.hdb
shiyan14\db\DAC.(6).cnf.cdb
shiyan14\db\DAC.(6).cnf.hdb
shiyan14\db\DAC.fit.qmsg
shiyan14\db\DAC.map.cdb
shiyan14\db\DAC.map.hdb
shiyan14\db\DAC.cmp.logdb
shiyan14\db\DAC.asm.qmsg
shiyan14\db\DAC.syn_hier_info
shiyan14\db\DAC.cmp.cdb
shiyan14\db\DAC.cmp.hdb
shiyan14\db\DAC.tan.qmsg
shiyan14\db\DAC.cmp.tdb
shiyan14\db\DAC.cmp0.ddb
shiyan14\db\DAC.sim.qmsg
shiyan14\db\DAC.sim.hdb
shiyan14\db\DAC.eds_overflow
shiyan14\db\DAC.sim.vwf
shiyan14\db\DAC.sim.rdb
shiyan14\db\wed.zsf
shiyan14\db
shiyan14

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