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des-verilog

  • Category : Other resource
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  • Update : 2008-10-13
  • Size : 66.13kb
  • Downloaded :0次
  • Author :杨云丰
  • About : 杨云丰
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Introduction - If you have any usage issues, please Google them yourself
des encryption algorithm to achieve the Verilog language
Packet file list
(Preview for download)
Packet : 73462677des-verilog.rar filelist
des
des\des
des\des\CVS
des\des\CVS\Root
des\des\CVS\Repository
des\des\CVS\Entries
des\des\bench
des\des\bench\CVS
des\des\bench\CVS\Root
des\des\bench\CVS\Repository
des\des\bench\CVS\Entries
des\des\bench\verilog
des\des\bench\verilog\CVS
des\des\bench\verilog\CVS\Root
des\des\bench\verilog\CVS\Repository
des\des\bench\verilog\CVS\Entries
des\des\bench\verilog\des3_test_ao.v
des\des\bench\verilog\des3_test_po.v
des\des\bench\verilog\des_test_ao.v
des\des\bench\verilog\des_test_po.v
des\des\doc
des\des\doc\CVS
des\des\doc\CVS\Root
des\des\doc\CVS\Repository
des\des\doc\CVS\Entries
des\des\doc\README.txt
des\des\rtl
des\des\rtl\CVS
des\des\rtl\CVS\Root
des\des\rtl\CVS\Repository
des\des\rtl\CVS\Entries
des\des\rtl\verilog
des\des\rtl\verilog\CVS
des\des\rtl\verilog\CVS\Root
des\des\rtl\verilog\CVS\Repository
des\des\rtl\verilog\CVS\Entries
des\des\rtl\verilog\area_opt
des\des\rtl\verilog\area_opt\CVS
des\des\rtl\verilog\area_opt\CVS\Root
des\des\rtl\verilog\area_opt\CVS\Repository
des\des\rtl\verilog\area_opt\CVS\Entries
des\des\rtl\verilog\area_opt\des.v
des\des\rtl\verilog\area_opt\des3.v
des\des\rtl\verilog\area_opt\key_sel.v
des\des\rtl\verilog\area_opt\key_sel3.v
des\des\rtl\verilog\common
des\des\rtl\verilog\common\CVS
des\des\rtl\verilog\common\CVS\Root
des\des\rtl\verilog\common\CVS\Repository
des\des\rtl\verilog\common\CVS\Entries
des\des\rtl\verilog\common\crp.v
des\des\rtl\verilog\common\sbox1.v
des\des\rtl\verilog\common\sbox2.v
des\des\rtl\verilog\common\sbox3.v
des\des\rtl\verilog\common\sbox4.v
des\des\rtl\verilog\common\sbox5.v
des\des\rtl\verilog\common\sbox6.v
des\des\rtl\verilog\common\sbox7.v
des\des\rtl\verilog\common\sbox8.v
des\des\rtl\verilog\perf_opt
des\des\rtl\verilog\perf_opt\CVS
des\des\rtl\verilog\perf_opt\CVS\Root
des\des\rtl\verilog\perf_opt\CVS\Repository
des\des\rtl\verilog\perf_opt\CVS\Entries
des\des\rtl\verilog\perf_opt\des.v
des\des\rtl\verilog\perf_opt\des3.v
des\des\rtl\verilog\perf_opt\key_sel.v
des\des\sim
des\des\sim\CVS
des\des\sim\CVS\Root
des\des\sim\CVS\Repository
des\des\sim\CVS\Entries
des\des\sim\rtl_sim
des\des\sim\rtl_sim\CVS
des\des\sim\rtl_sim\CVS\Root
des\des\sim\rtl_sim\CVS\Repository
des\des\sim\rtl_sim\CVS\Entries
des\des\sim\rtl_sim\bin
des\des\sim\rtl_sim\bin\CVS
des\des\sim\rtl_sim\bin\CVS\Root
des\des\sim\rtl_sim\bin\CVS\Repository
des\des\sim\rtl_sim\bin\CVS\Entries
des\des\sim\rtl_sim\bin\Makefile
des\des\sim\rtl_sim\run
des\des\sim\rtl_sim\run\CVS
des\des\sim\rtl_sim\run\CVS\Root
des\des\sim\rtl_sim\run\CVS\Repository
des\des\sim\rtl_sim\run\CVS\Entries
des\des\syn
des\des\syn\CVS
des\des\syn\CVS\Root
des\des\syn\CVS\Repository
des\des\syn\CVS\Entries
des\des\syn\bin
des\des\syn\bin\CVS
des\des\syn\bin\CVS\Root
des\des\syn\bin\CVS\Repository
des\des\syn\bin\CVS\Entries
des\des\syn\bin\comp_ao.dc
des\des\syn\bin\comp_ao3.dc
des\des\syn\bin\comp_po.dc
des\des\syn\bin\comp_po3.dc
des\des\syn\bin\design_spec_ao.dc
des\des\syn\bin\design_spec_ao3.dc
des\des\syn\bin\design_spec_po.dc
des\des\syn\bin\design_spec_po3.dc
des\des\syn\bin\lib_spec.dc
des\des\syn\bin\read_ao.dc
des\des\syn\bin\read_ao3.dc
des\des\syn\bin\read_po.dc
des\des\syn\bin\read_po3.dc
des\des\syn\log
des\des\syn\log\CVS
des\des\syn\log\CVS\Root
des\des\syn\log\CVS\Repository
des\des\syn\log\CVS\Entries
des\des\syn\out
des\des\syn\out\CVS
des\des\syn\out\CVS\Root
des\des\syn\out\CVS\Repository
des\des\syn\out\CVS\Entries
des\des\syn\run
des\des\syn\run\CVS
des\des\syn\run\CVS\Root
des\des\syn\run\CVS\Repository
des\des\syn\run\CVS\Entries
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