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Verilog_Single_Cycle_CPU_check

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-09-15
  • Size : 9kb
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  • Author ：RogerBryant
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Introduction - If you have any usage issues, please Google them yourself
A single cycle CPU written in Verilog for group experiment.
Packet file list
(Preview for download)
FilenameSizeUpdate
adder.v 639 2017-11-26
ALU.v 1677 2017-12-08
ALU_dec.v 1080 2017-12-08
Controller.v 1037 2017-12-07
Datapath.v 2109 2017-12-07
DM.v 1018 2017-11-26
EXT.v 923 2017-11-26
GRF.v 1302 2017-11-28
IF_RAM.v 734 2017-12-08
IFU.v 870 2017-11-27
left_2bits.v 641 2017-11-26
Main_dec.v 2169 2017-12-08
mips.v 1225 2017-12-07
Mux_2bits.v 907 2017-11-26
Mux_4bits.v 1129 2017-11-26
NextPC.v 1417 2017-11-26
PCreg.v 781 2017-12-08
Sign_ext.v 667 2017-11-26
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