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VerilogUart_Modelsim

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  • Category : VHDL-FPGA-Verilog
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  • Update : 2018-10-27
  • Size : 46kb
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  • Author ：myBuf
  • About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
use Verilog Write UART Program, Modelsim simmulate the project
Packet file list
(Preview for download)
FilenameSizeUpdate
UART 0 2018-10-22
UART\src 0 2018-10-22
UART\src\sim 0 2018-10-27
UART\src\sim\modelsim.ini 75872 2018-10-22
UART\src\sim\run.do 191 2018-10-22
UART\src\sim\testbench_uart.v 2013 2018-10-22
UART\src\sim\wave.do 2094 2018-10-22
UART\src\sim\work 0 2018-10-22
UART\src\sim\work\_info 687 2018-10-22
UART\src\sim\work\_temp 0 2018-10-27
UART\src\sim\work\_vmake 26 2018-10-22
UART\src\sim\work\testbench 0 2018-10-22
UART\src\sim\work\testbench\_primary.dat 1537 2018-10-22
UART\src\sim\work\testbench\_primary.dbs 1427 2018-10-22
UART\src\sim\work\testbench\_primary.vhd 689 2018-10-22
UART\src\sim\work\testbench\verilog.asm64 25808 2018-10-22
UART\src\sim\work\testbench\verilog.rw64 1011 2018-10-22
UART\src\sim\work\uart 0 2018-10-22
UART\src\sim\work\uart\_primary.dat 3522 2018-10-22
UART\src\sim\work\uart\_primary.dbs 3725 2018-10-22
UART\src\sim\work\uart\_primary.vhd 1079 2018-10-22
UART\src\sim\work\uart\verilog.asm64 61568 2018-10-22
UART\src\sim\work\uart\verilog.rw64 2093 2018-10-22
UART\src\uart.v 5033 2018-10-22
UART\~$rilog串口Modelsim仿真.doc 162 2018-10-22
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