A Relatively Simple RISC CPU design source with detailed documentation. ModelSim simulation can be carried out, and they can Synplify synthesis.

Packet : 17869320arelativelysimplerisccpu.rar filelist
ARelativelySimpleRISCCPU\risc_cpu\cpu_top.v
ARelativelySimpleRISCCPU\risc_cpu\counter.v
ARelativelySimpleRISCCPU\risc_cpu\machine.v
ARelativelySimpleRISCCPU\risc_cpu\machinectl.v
ARelativelySimpleRISCCPU\risc_cpu\ram.v
ARelativelySimpleRISCCPU\risc_cpu\register.v
ARelativelySimpleRISCCPU\risc_cpu\rom.v
ARelativelySimpleRISCCPU\risc_cpu\ datactl.v
ARelativelySimpleRISCCPU\risc_cpu\accum.v
ARelativelySimpleRISCCPU\risc_cpu\addr_decode.v
ARelativelySimpleRISCCPU\risc_cpu\adr.v
ARelativelySimpleRISCCPU\risc_cpu\alu.v
ARelativelySimpleRISCCPU\risc_cpu\clk_gen.v
ARelativelySimpleRISCCPU\risc_cpu\test_cpu.v
ARelativelySimpleRISCCPU\risc_cpu\datactl.v
ARelativelySimpleRISCCPU\risc_cpu\Risc_cpu设计说明文档.doc
ARelativelySimpleRISCCPU\risc_cpu
ARelativelySimpleRISCCPU

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