I have written a Verilog clock procedures, in Xilinx s ISE simulation through

Packet : 57578854clock.rar filelist
clock\clock.ise
clock\__ISE_repository_clock.ise_.lock
clock\clock_test.xwv
clock\clock_test.tfw
clock\clock_test.ant
clock\clock_test.jhd
clock\xilinxsim.ini
clock\isim.log
clock\clock.ise_ISE_Backup
clock\clock_test_isim_beh.exe
clock\isim.hdlsourcefiles
clock\clock2_test.v
clock\clock2_test_v_stx.prj
clock\clock2_test_bencher.prj
clock\clock2_test.xwv
clock\clock2_test.xwv_bak
clock\clock2_test.tfw
clock\clock2_test.ant
clock\clock2_test.tbw
clock\clock2_test.jhd
clock\clock2_test_beh.prj
clock\clock2_test_isim_beh.exe
clock\tmpRTVStore.xwv
clock\clock.v
clock\clock_summary.html
clock\clock_stx.prj
clock\clock_test_bencher.prj
clock\clock_test.xwv_bak
clock\clock_test.tbw
clock\clock_test_beh.prj
clock\isim.cmd
clock\isimwavedata.xwv
clock\isim.tmp_save\_1
clock\isim\work\hdllib.ref
clock\isim\work\hdpdeps.ref
clock\isim\work\clock2__test\clock2__test.h
clock\isim\work\clock2__test\xsimclock2__test.cpp
clock\isim\work\clock2__test\mingw\clock2__test.obj
clock\isim\work\vlg1D\clock2__test.bin
clock\isim\work\glbl\glbl.h
clock\isim\work\glbl\mingw\glbl.obj
clock\isim\work\vlg2D\glbl.bin
clock\isim\work\clock__test\clock__test.h
clock\isim\work\clock__test\xsimclock__test.cpp
clock\isim\work\clock__test\mingw\clock__test.obj
clock\isim\work\vlg43\clock__test.bin
clock\isim\work\clock\clock.h
clock\isim\work\clock\mingw\clock.obj
clock\isim\work\vlg20\clock.bin
clock\isim\temp\hdllib.ref
clock\isim\temp\hdpdeps.ref
clock\isim\temp\vlg26\clock2__test__v.bin
clock\isim\temp\vlg2D\glbl.bin
clock\isim\temp\vlg20\clock.bin
clock\_xmsgs\fuse.xmsgs
clock\isim\work\clock2__test\mingw
clock\isim\work\glbl\mingw
clock\isim\work\clock__test\mingw
clock\isim\work\clock\mingw
clock\isim\work\clock2__test
clock\isim\work\vlg1D
clock\isim\work\glbl
clock\isim\work\vlg2D
clock\isim\work\clock__test
clock\isim\work\vlg43
clock\isim\work\clock
clock\isim\work\vlg20
clock\isim\temp\vlg26
clock\isim\temp\vlg2D
clock\isim\temp\vlg20
clock\isim\work
clock\isim\temp
clock\isim.tmp_save
clock\isim
clock\_xmsgs
clock

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