opencores the source, to help engage everyone down, and they hope to have everyone help

Packet : 41695059i2c.rar filelist
rtl\vhdl\readme
doc\src\I2C_specs.doc
sim\i2c_verilog\run\ncverilog.log
software\include\oc_i2c_master.h
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sim\i2c_verilog\run\INCA_libs\CVS\Entries
sim\i2c_verilog\run\waves\CVS\Entries
software\drivers\CVS\Entries
verilog\CVS\Entries
vhdl\CVS\Entries
sim\i2c_verilog\CVS\Entries
bench\CVS\Entries
sim\CVS\Entries
rtl\CVS\Entries
software\CVS\Entries
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sim\i2c_verilog\CVS\Repository
software\drivers\CVS\Repository
software\include\CVS\Repository
sim\i2c_verilog\run\CVS\Repository
sim\i2c_verilog\run\waves\CVS\Repository
sim\i2c_verilog\run\INCA_libs\CVS\Repository
bench\CVS\Root
bench\verilog\CVS\Root
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doc\CVS\Root
doc\src\CVS\Root
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rtl\CVS\Root
rtl\verilog\CVS\Root
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sim\i2c_verilog\run\CVS\Root
sim\i2c_verilog\run\INCA_libs\CVS\Root
sim\i2c_verilog\run\waves\CVS\Root
software\CVS\Root
software\drivers\CVS\Root
software\include\CVS\Root
verilog\CVS\Root
vhdl\CVS\Root
sim\i2c_verilog\run\run
sim\i2c_verilog\run\ncverilog.key
doc\i2c_specs.pdf
rtl\verilog\i2c_master_bit_ctrl.v
rtl\verilog\i2c_master_byte_ctrl.v
rtl\verilog\i2c_master_defines.v
rtl\verilog\i2c_master_top.v
bench\verilog\i2c_slave_model.v
bench\verilog\spi_slave_model.v
rtl\verilog\timescale.v
bench\verilog\tst_bench_top.v
bench\verilog\wb_master_model.v
sim\i2c_verilog\run\bench.vcd
rtl\vhdl\I2C.VHD
rtl\vhdl\i2c_master_bit_ctrl.vhd
rtl\vhdl\i2c_master_byte_ctrl.vhd
rtl\vhdl\i2c_master_top.vhd
rtl\vhdl\tst_ds1621.vhd
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