Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.

Packet : 37724080signal_cpu_sort.rar filelist
signal_cpu_sort\Add.v
signal_cpu_sort\Alu.v
signal_cpu_sort\Alu_control.v
signal_cpu_sort\Control.v
signal_cpu_sort\Data_memory.v
signal_cpu_sort\Instruction_memory.v
signal_cpu_sort\Line_control.v
signal_cpu_sort\Pc.v
signal_cpu_sort\Registers.v
signal_cpu_sort\Sign_extend.v
signal_cpu_sort\Single_cycle_cpu.v
signal_cpu_sort\test.prj
signal_cpu_sort\test.v
signal_cpu_sort\testbranch.v
signal_cpu_sort

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