32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only

Packet : 794195332位-33m 从模式(target)pci接口参考设计_lattice.rar filelist
32位-33M 从模式(target)PCI接口参考设计_lattice\state_machine.v
32位-33M 从模式(target)PCI接口参考设计_lattice\config_mux.v
32位-33M 从模式(target)PCI接口参考设计_lattice\glue.v
32位-33M 从模式(target)PCI接口参考设计_lattice\pargen.v
32位-33M 从模式(target)PCI接口参考设计_lattice\pci_top.v
32位-33M 从模式(target)PCI接口参考设计_lattice\retry_count.v
32位-33M 从模式(target)PCI接口参考设计_lattice\base_addr_chk.v
32位-33M 从模式(target)PCI接口参考设计_lattice\rd1008.pdf
32位-33M 从模式(target)PCI接口参考设计_lattice\tstbench.zip
32位-33M 从模式(target)PCI接口参考设计_lattice\32位-33M 从模式(target)PCI接口参考设计_lattice说明.pdf
32位-33M 从模式(target)PCI接口参考设计_lattice

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