Input format: GraphML : graphml format contains nodes and edges of the graph. Output format: Testing: Done by VLSI TEAM

Packet : tech-mapping-master.zip filelist
tech-mapping-master/
tech-mapping-master/README
tech-mapping-master/examples/
tech-mapping-master/examples/2inand.blif
tech-mapping-master/examples/2inand.xml
tech-mapping-master/examples/2or.blif
tech-mapping-master/examples/2or.xml
tech-mapping-master/examples/3in.blif
tech-mapping-master/examples/3in.xml
tech-mapping-master/examples/alu.xml
tech-mapping-master/examples/eg1.xml
tech-mapping-master/reading/
tech-mapping-master/reading/Document_reading.txt
tech-mapping-master/src/
tech-mapping-master/src/library/
tech-mapping-master/src/library/2_in_nor.xml
tech-mapping-master/src/library/2nand.xml
tech-mapping-master/src/library/3_in_nand.xml
tech-mapping-master/src/library/3_in_nor.xml
tech-mapping-master/src/library/4_in_nand.xml
tech-mapping-master/src/library/4_in_nor.xml
tech-mapping-master/src/library/not.xml
tech-mapping-master/src/techMapping.py

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