An algorithm to route the wires in integrated circuits. The router handles 2 point nets, non-unit costs in the routing g

Packet : vlsi-cad-router-master.zip filelist
vlsi-cad-router-master/
vlsi-cad-router-master/README.md
vlsi-cad-router-master/cell.py
vlsi-cad-router-master/grids/
vlsi-cad-router-master/grids/bench1.grid
vlsi-cad-router-master/grids/bench2.grid
vlsi-cad-router-master/grids/bench3.grid
vlsi-cad-router-master/grids/bench4.grid
vlsi-cad-router-master/grids/bench5.grid
vlsi-cad-router-master/grids/fract2.grid
vlsi-cad-router-master/grids/industry1.grid
vlsi-cad-router-master/grids/primary1.grid
vlsi-cad-router-master/grids/toy1.grid
vlsi-cad-router-master/netlist.py
vlsi-cad-router-master/netlists/
vlsi-cad-router-master/netlists/bench1.nl
vlsi-cad-router-master/netlists/bench2.nl
vlsi-cad-router-master/netlists/bench3.nl
vlsi-cad-router-master/netlists/bench4.nl
vlsi-cad-router-master/netlists/bench5.nl
vlsi-cad-router-master/netlists/fract2.nl
vlsi-cad-router-master/netlists/industry1.nl
vlsi-cad-router-master/netlists/primary1.nl
vlsi-cad-router-master/netlists/toy1.nl
vlsi-cad-router-master/outputs/
vlsi-cad-router-master/outputs/bench1.out
vlsi-cad-router-master/outputs/bench2.out
vlsi-cad-router-master/outputs/bench3.out
vlsi-cad-router-master/outputs/bench4.out
vlsi-cad-router-master/outputs/bench5.out
vlsi-cad-router-master/outputs/fract2.out
vlsi-cad-router-master/outputs/primary1.out
vlsi-cad-router-master/router_main.py
vlsi-cad-router-master/routing_grid.py
vlsi-cad-router-master/testcase.py
vlsi-cad-router-master/wavefront.py

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