Network on Chip design using XY routing algorithm with FPGA implementation (Verilog)

Packet : NoC_Verilog_Codes.rar filelist
XY_Router.v
Aribiter_B.v
BUFFER_FIFO_R.v
floating_buffer_R.v
floatingbuffer_controller_B.v
Mux_21_B.v
Mux_41_B.v
mux21_B.v
Network_on_chip_B.v
RAMF_R.v
Router_tb.v
Switching_matrix_B.v

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