Lattice Semiconductor Corp. I2C Master Controller Reference Design RD1005 release 2013

Packet : rd1005_i2c_master_controller_2013_vhd.zip filelist
rd1005_i2c_master_controller_2013_vhd/
rd1005_i2c_master_controller_2013_vhd/rd1005/
rd1005_i2c_master_controller_2013_vhd/rd1005/docs/
rd1005_i2c_master_controller_2013_vhd/rd1005/docs/i2c_bus_specification.pdf
rd1005_i2c_master_controller_2013_vhd/rd1005/docs/rd1005.pdf
rd1005_i2c_master_controller_2013_vhd/rd1005/docs/rd1005_readme.txt
rd1005_i2c_master_controller_2013_vhd/rd1005/docs/revision_history.xlsx
rd1005_i2c_master_controller_2013_vhd/rd1005/project/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/verilog/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/verilog/ecp3_verilog.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/verilog/ecp3_verilog.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/verilog/ecp3_verilog1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/vhdl/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/vhdl/ecp3_vhdl.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/vhdl/ecp3_vhdl.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp3/vhdl/ecp3_vhdl1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/verilog/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/verilog/ecp5_verilog.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/verilog/ecp5_verilog.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/verilog/ecp5_verilog1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/vhdl/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/vhdl/ecp5_vhdl.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/vhdl/ecp5_vhdl.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/ecp5/vhdl/ecp5_vhdl1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/verilog/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/verilog/lptm_verilog.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/verilog/lptm_verilog.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/verilog/lptm_verilog1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/vhdl/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/vhdl/lptm_vhdl.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/vhdl/lptm_vhdl.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/lptm/vhdl/lptm_vhdl1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/verilog/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/verilog/xo_verilog.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/verilog/xo_verilog.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/verilog/xo_verilog1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/vhdl/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/vhdl/xo_vhdl.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/vhdl/xo_vhdl.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo/vhdl/xo_vhdl1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/verilog/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/verilog/xo2_verilog.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/verilog/xo2_verilog.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/verilog/xo2_verilog1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/vhdl/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/vhdl/xo2_vhdl.ldf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/vhdl/xo2_vhdl.lpf
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo2/vhdl/xo2_vhdl1.sty
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/.run_manager.ini
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/promote.xml
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/reportview.xml
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/._Real_._Math_.vhd
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/Edfmap.ini
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compilation.order
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compile/
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compile.cfg
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compile/contents.lib~test1
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compile/contents.lib~work
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compile/sources.sth
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compile/test1.epr
rd1005_i2c_master_controller_2013_vhd/rd1005/project/xo3l/verilog/test1/compile/test1.erf

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