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Counter up and down

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2024-10-03
  • Size : 34.16kb
  • Downloaded :0次
  • Author :w3bpunk
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
vhdl code + testbench of up and down counter based on t-trigger
Packet file list
(Preview for download)
Packet : counter_upndown.rar filelist
livesem6test/library.cfg
livesem6test/livesem6/bde.set
livesem6test/livesem6/compilation.order
livesem6test/livesem6/compile/contents.lib~livesem6
livesem6test/livesem6/compile/livesem6.epr
livesem6test/livesem6/compile/livesem6.erf
livesem6test/livesem6/compile/livesem6.top
livesem6test/livesem6/compile/sources.sth
livesem6test/livesem6/compile/vcom.cmd
livesem6test/livesem6/compile.cfg
livesem6test/livesem6/Edfmap.ini
livesem6test/livesem6/livesem6/0livesem6.mgf
livesem6test/livesem6/livesem6/1livesem6.mgf
livesem6test/livesem6/livesem6/3livesem6.mgf
livesem6test/livesem6/livesem6/elaboration.log
livesem6test/livesem6/livesem6/livesem6.lib
livesem6test/livesem6/livesem6.adf
livesem6test/livesem6/livesem6.duser
livesem6test/livesem6/livesem6.wsp
livesem6test/livesem6/log/console.log
livesem6test/livesem6/projlib.cfg
livesem6test/livesem6/src/counter_up_down.vhd
livesem6test/livesem6/src/counter_up_down_tb.vhd
livesem6test/livesem6/src/modelling.asdb
livesem6test/livesem6/src/modelling.awc
livesem6test/livesem6/src/t_trig.vhd
livesem6test/livesem6/src/wave.asdb
livesem6test/livesem6/synthesis.order
livesem6test/livesem6test.aws
livesem6test/livesem6test.wsw
livesem6test/livesem6/compile
livesem6test/livesem6/livesem6
livesem6test/livesem6/log
livesem6test/livesem6/src
livesem6test/livesem6
livesem6test
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