this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.

Packet : 45666032ref-sdr-sdram-verilog.zip filelist
doc/
readme_sdr_sdram.txt
sdr_sdram.pdf
simulation/
simulation/sdr_sdram_tb.v
source/
source/altclklock.v
source/Command.v
source/compile_all.v
source/control_interface.v
source/Params.v
source/PLL1.v
source/sdr_data_path.v
source/sdr_sdram.v

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